Clock generator using PLL and information processing system usin

Details Clock generator using PLL and information processing system usin Clock generator using PLL and information processing system usin

1990-03-02

1994-10-25

Shaw, Dale M.

Oscillators

Relaxation oscillators

331 10, G06F 106

Patent

active

053597273

ABSTRACT:
In a clock generating apparatus or clock generator employing PLL (phase-locked loop) by controlling a VCO (voltage controlled oscillator) in response to an output obtained by phase-comparing a clock signal based on an output signal of the VCO with an externally applied timing signal, a range of an oscillating frequency of VCO is varied in accordance with a frequency variation in the timing signal. A clock generating apparatus is provided for each of plural information processing sections, so as to surely synchronize operations of data processings including data transfers between the respective sections. When a clock signal is distributed to each of the information processing sections, the clock signal outputted from the distributing circuit is phase-compared in order to control the VCO. A charge pump circuit for a low-pass filter is employed and a frequency/current converting circuit for controlling VCO is also employed, which are suitable in order for generating a clock signal in a range of, for instance, 1 to 100 MHz in response to the frequency variation in the timing signal.

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