Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Rectangular or pulse waveform width control
Reexamination Certificate
2002-07-22
2004-08-31
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Rectangular or pulse waveform width control
C327S291000, C327S298000
Reexamination Certificate
active
06784709
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device and, more particularly, to a clock generator to produce internal clock signals with a controlled pulse width in a synchronous semiconductor memory device.
DESCRIPTION OF THE RELATED ARTS
To increase the operation speed of highly integrated semiconductor memory devices, synchronous memory devices, which are synchronized with system clock signals from a memory controller, have been developed.
Read and write operations of asynchronous semiconductor memory devices are performed in response to row address strobe and column address strobe signals without a system clock signal while the synchronous semiconductor memory devices are synchronized with the fast clock signal from the memory controller. Accordingly, the operation speed of the synchronous semiconductor memory device is typically faster than that of the asynchronous semiconductor memory device. Moreover, in the high-speed central processing unit (CPU), the synchronous semiconductor memory devices, such as double data rate (DDR) SDRAMs and Rambus DRAMs, have been proposed as next generation memory devices allowing high-speed operation of the CPU.
Meanwhile, the synchronous semiconductor memory device operates in synchronization with the system clock signal and this system clock signal is changed into an internal clock signal by an internal clock generator in order that an external clock signal from the memory controller is employed in the synchronous semiconductor memory devices. This clock generator, which carries out a relatively stable operation in spite of changes in temperature or voltage etc, may play an important part of the synchronous semiconductor memory devices.
Referring to
FIG. 1
, a conventional clock generator of a semiconductor memory device includes a clock input unit
2
receiving an external clock signal Clock and a reference voltage Vref and a clock driver unit
4
receiving a clock signal Clkp
2
from the clock input unit
2
and outputting an internal clock signal Clkp
4
. As with the general synchronous apparatus, the synchronous semiconductor memory device operates on a reference pulse. Here, the internal clock signal Clkp
4
is used as the reference pulse associated with the production of employed signals and the control thereof.
The detailed circuit diagram of the clock input unit
2
is shown in FIG.
2
. The clock input unit
2
includes a differential amplifier
12
to amplify a difference between the external clock signal Clock and the reference voltage Vref. The amplified voltage signal (clock signal Clkp
0
) from the differential amplifier
12
is delayed in a delay unit
14
. A NAND gate
16
receives both the delayed signal and the amplified voltage signal Clkp
0
, and then the clock signal Clkp
2
is finally produced in an inverter
18
. The delay unit
14
determines the pulse width of the clock signal Clkp
2
.
The detailed configuration of the clock driver unit
4
of
FIG. 1
is shown in FIG.
3
. Referring to
FIG. 3
, the clock driver
4
includes two CMOS inverters
22
and
24
and a feedback loop, which comprises a delay unit
26
, inverters
28
and
30
and PMOS and NMOS transistors
32
and
34
respectively connected to the output terminals of the CMOS inverters
22
and
24
. Since the feedback loop is connected to the output terminals of each of the CMOS inverters
22
and
24
, the clock driver unit
4
may have different drivabilities depending on the voltage levels of the output internal clock signal Clkp
4
. The delay width of the delay unit
26
is determined by an amount of delay in the delay unit
14
in the clock input unit
2
where the delay units
14
and
26
may have the same delay time.
Referring to
FIGS. 2 and 3
, the differential amplifier
12
generates the second clock signal Clkp
0
when the external clock signal Clock is inputted into the clock input unit
2
. The second clock signal Clkp
0
is delayed in the delay unit
14
having a predetermined delay value and then the clock signal Clkp
2
is produced via the NAND gate
16
and the inverter
18
. Next, the clock signal Clkp
2
is amplified by the clock driver unit
4
having the two CMOS inverters
22
and
24
to produce the final internal clock signal Clkp
4
. The pulse width of the clock signal Clkp
4
is determined by the delay unit
26
of the feedback loop.
However, there is a problem in that the delay and the pulse width of the clock signal Clkp
4
are unstable, which in turn cause the control and other signals generated by the clock signal Clkp
4
to be unstable. That is, referring to
FIG. 4
, as the supply voltage is changed into 4.0V, 3.0V, 2.5V or 2.0V, the delayed value and the pulse width are considerably changed. Moreover, variation in the delayed value and the pulse width becomes more sensitive with changes in temperature and process variables.
This instability caused by the clock signal Clkp
4
, destabilize other control signals and circuits, making it difficult to provide an appropriate timing margin for the internal circuits.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a clock generator to produce internal clock signals with a controlled pulse width.
It is another object of the present invention to provide a clock generator producing stable pulse signal even if there is a variation in voltage, temperature and process.
In accordance with an aspect of the present invention, there is a clock generating circuit in a semiconductor device comprising: clock input means for receiving an external clock signal, a reference voltage signal and an option signal, and for outputting first and second clock signals; clock driving means for receiving the first clock signal from the clock input means and for outputting an internal clock signal in response to the option signal; and a detecting means for receiving the second clock signal from the clock input means and for outputting the option signal in response to a control signal.
In accordance with another aspect of the present invention, there is a clock generating circuit in a semiconductor device comprising: clock input means for receiving an external clock signal, a reference voltage signal and an option signal, and for outputting first and second clock signals; clock driving means for receiving the first clock signal and outputting an internal clock signal in response to the option signal; a detecting means for receiving the second clock signal and outputting the option signal in response to a control signal; and means for outputting the control signal to determine operation of the clock generating circuit in response to command signal from a system controller.
In accordance with still another aspect of the present invention, there is a clock generating circuit in a semiconductor device comprising: clock input means for receiving an external clock signal, a reference voltage signal and an option signal, and for outputting first and second clock signals; clock driving means for receiving the first clock signal and outputting an internal clock signal in response to the option signal; a mode register outputting the control signal in response to a command signal from a system controller; means for producing the option signal to control a pulse width of the internal clock signal, wherein the option signal increases the pulse width of the internal clock signal at high voltages and decreases the pulse width of the internal clock signal at low voltages.
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Hynix / Semiconductor Inc.
Jacobson & Holman PLLC
Nguyen Hai L.
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