Clock generator in which external oscillator is disabled after i

Details Clock generator in which external oscillator is disabled after i Clock generator in which external oscillator is disabled after i

1997-11-05

1999-08-10

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

With intermittent comparison controls

331 18, 331 49, 331 74, 331158, 331DIG2, 331DIG3, H03B 536, H03L 7095

Patent

active

059364734

ABSTRACT:
An oscillation circuit stops the oscillation of an external oscillator to reduce the current consumed when a frequency lower than the inherent frequency of the external oscillator is supplied to a microcomputer. A PLL circuit 37 generates a second clock 45 from a first clock 23 output by an oscillation circuit 1. A PLL lock signal 47 is changed from a first level to a second level when the second clock 45 is generated. A selector 39 outputs the second clock 45 as an internal clock 13 when the PLL lock signal 47 is at the second level. The operation of an oscillator 9 is stopped when the PLL lock signal 47 is at the second level.

REFERENCES:
patent: 5126695 (1992-06-01), Abe
patent: 5606293 (1997-02-01), Matsui et al.
patent: 5623234 (1997-04-01), Shaik et al.
patent: 5754081 (1998-05-01), Kuroiwa et al.

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