Clock generator in PCM signal reproducing apparatus

Details Clock generator in PCM signal reproducing apparatus Clock generator in PCM signal reproducing apparatus

1980-12-10

1982-09-21

Safourek, Benedict V.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

360 36, 375120, H03B 304, H04N 505, H04N 578

Patent

active

043510000

ABSTRACT:
A PCM signal reproducing apparatus processes PCM audio signals including vertical synchronizing signals and horizontal synchronizing signals for reproducing purposes. The oscillation output of a voltage controlled oscillator is frequency divided in synchronism with the horizontal synchronizing signals to develop clock signals. A frequency divider circuit is provided to frequency divide the clock signals and develop signals to be compared. While the clock signals or its frequency divided signals being counted, narrower pulses whose width is shorter than the interval of the vertical synchronizing signals and broader pulses whose width is longer than the interval of the vertical synchronizing signals are generated. An OR gate receives as its inputs the vertical synchronizing signals and the narrower pulses, while an AND gate receives as its inputs the output of the OR gate and the broader pulses. The output of the AND gate is supplied as a reference input to a phase comparator which in turn compares the reference input and the signals to be compared obtained from the frequency divider circuit and then controls the voltage controlled oscillator.

REFERENCES:
patent: 4203076 (1980-05-01), Yamishita
patent: 4253116 (1981-02-01), Rodgers

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