Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2007-06-05
2007-06-05
Yoha, Connie C. (Department: 2827)
Static information storage and retrieval
Addressing
Sync/clocking
C327S158000, C327S156000, C365S226000
Reexamination Certificate
active
11250600
ABSTRACT:
A clock generator having a delay locked loop and a duty cycle correction circuit. The delay locked loop adjusts a first adjustable delay circuit to generate a first output clock signal that is synchronized with a first input clock signal and adjusts a second adjustable delay circuit to provide a delay that is equal to the first adjustable delay circuit. A duty cycle correction circuit is coupled to the first and second inputs of the delay locked loop and further coupled to the second adjustable delay circuit. The duty cycle correction circuit is configured to determine a duty cycle error of at least one of the first and second input clock signals and adjust the second adjustable delay circuit to provide a corrected delay compensating for the duty cycle error.
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Dorsey & Whitney LLP
Yoha Connie C.
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