Dynamic information storage or retrieval – Binary pulse train information signal – Binary signal gain processing
Reexamination Certificate
1998-09-23
2004-10-26
Psitos, Aristotelis M. (Department: 2653)
Dynamic information storage or retrieval
Binary pulse train information signal
Binary signal gain processing
C369S059210, C369S059220
Reexamination Certificate
active
06810000
ABSTRACT:
This application claims the benefit of Japanese Patent Application No. 9-258088, filed Sep. 24, 1997, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a recorded information reproduction apparatus and, more particularly, to a clock generator for generating a clock signal synchronized in phase with recorded information according to a reading signal read from a recording medium.
2. Description of the Related Art
FIG. 1
is a diagram showing structure of a recorded information reproduction apparatus.
Referring to
FIG. 1
, a pickup
1
reads recorded information from a recording disk
3
driven by a spindle motor
2
and a reading signal obtained at this time is supplied to a head amplifier
4
. The head amplifier
4
supplies a reading signal amplified at a desired level to an A/D converter
5
. The A/D converter
5
samples this amplified reading signal at a timing of a clock signal successively supplied from a PLL circuit
10
and supplies a reading sample value sequence to each of the PLL, circuit
10
and a Viterbi decoder
30
.
A phase detecting circuit
11
of the PLL circuit
10
detects a phase error existing in the aforementioned reading signal based on a reading sample value sequence supplied successively from the A/D converter
5
and supplies a phase error signal corresponding to this phase error to an LPF (low-pass filter)
12
. The LPF
12
supplies an average phase error signal obtained by averaging the phase error signal to the VCO (voltage control oscillator)
13
. The VCO
13
generates a clock signal having a frequency corresponding to this average phase error signal and supplies this signal to the A/D converter
5
. The Viterbi decoder
30
obtains the most certain binary reproduced data possible based on the reading sample value sequence supplied successively from the A/D converter
5
.
However, if a reading signal obtained by reading by the aforementioned pickup
1
is under an influence of crosstalk, proper phase error detection is disabled in the phase detecting circuit
11
of the PLL circuit
10
so that jitter occurs in the generated clock signal.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a clock generator that substantially obviates one or more of the problems due to limitations and disadvantages of the related art. An object of the present invention is to provide a clock generator capable of generating a clock signal synchronized properly in phase with recorded information based on a reading signal even in the situation where the reading signal is affected by crosstalk.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages, and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention provides a clock generator in a recorded information reproduction apparatus for reproducing recorded information from a recording medium, including a pickup for producing a reading signal by reading a recording track of the recording medium, a sampling circuit for sampling the reading signal at a timing corresponding to a clock signal and producing a reading sample value sequence, a crosstalk removing circuit for removing crosstalk components from the reading sample value sequence and producing a crosstalk-removed reading sample value sequence, the crosstalk components being present in recording tracks adjacent to the recording track read by the pickup, a phase detecting circuit for detecting a phase error existing in the reading signal based on the crosstalk-removed reading sample value sequence, and a clock signal generating circuit for generating the clock signal based on the phase error.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5280466 (1994-01-01), Tomita
patent: 5455813 (1995-10-01), Hayashi
patent: 5606540 (1997-02-01), Hayashi
patent: 5657312 (1997-08-01), Hayashi
patent: 5663945 (1997-09-01), Hayashi et al.
patent: 5835467 (1998-11-01), Tomita et al.
patent: 559493 (1993-08-01), None
patent: 3-156729 (1991-07-01), None
patent: 3-178040 (1991-08-01), None
patent: 9-320200 (1997-12-01), None
English translation, JP 3-178040.
No affiliations
Pioneer Electronic Corporation
Psitos Aristotelis M.
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