Clock generator for generating internal clock signal...

Details Clock generator for generating internal clock signal... Clock generator for generating internal clock signal...

2002-05-22

2003-05-27

Callahan, Timothy P. (Department: 2816)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

C327S158000

Reexamination Certificate

active

06570456

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a clock generating circuit, and more particularly to a clock synchronizing circuit for generating an internal clock signal synchronized in phase with a reference clock signal.
2. Description of the Background Art
FIG. 18
shows an example of a configuration of a conventional clock generator. By way of example, the figure shows a configuration of a phase synchronizing circuit (phase locked loop circuit (PLL circuit)) including a voltage controlled oscillating circuit of a ring oscillator type.
As shown in
FIG. 18
, the clock generator includes: a phase comparison circuit PH for comparing a phase of a reference clock signal having a predetermined cycle C and a phase of a recovered clock signal CO and producing a signal according to the phase difference; a charge pump/low pass filter CPLP including a charge pump performing a charge pumping operation according to the phase difference detection signal produced from the phase comparison circuit PH to generate a control voltage and a low pass filter for removing a high frequency component of the control voltage produced from the charge pump; a bias controlling circuit BK for generating bias voltages V
1
and V
2
in accordance with the control voltage from the charge pump/low pass filter; a voltage controlled oscillation circuit O having an oscillation frequency controlled in accordance with the bias voltages V
1
and V
2
from the bias control circuit BK. voltages produced by the charge pump. Bias control circuit BK generates bias voltages V
1
and V
2
according to the control voltages produced by charge pump/low pass filter CPLP. Voltage controlled oscillation circuit O controls oscillation frequencies according to bias voltages V
1
and V
2
produced by Bias control circuit BK.
Phase comparison circuit PH compares the phases of reference clock signal C and recovered clock signal CO, and produces an up-signal for increasing a frequency of the recovered clock signal CO or a down-signal for decreasing the frequency of the recovered clock signal CO in accordance with the phase difference.
In charge pump/low pass filter CPLP, the charge pump performs charge/discharge operation in response to the up- or down-signal received from phase comparison circuit PH, and the low pass filter performs the integration of the charged potential due to the charge/discharge current generated by the charge pump, for generating the control voltage. The low pass filter is normally called a loop filter.
Bias control circuit BK receives the control voltage from charge pump/low pass filter CPLP, and generates bias voltages V
1
and V
2
for adjusting the oscillation frequency of oscillation circuit O.
Oscillation circuit O includes an odd-number of stages of delay cells D
1
to Dn coupled in a ring form. In delay cells D
1
to Dn, a cell signal of a preceding stage is sequentially transferred to a delay cell of a subsequent delay cell, and the recovered clock signal CO generated from the final-stage delay cell Dn is fed-back to the delay cell D
1
of the initial stage. Delay cells D
1
to Dn each have an identical configuration, and therefore, in
FIG. 18
, reference characters are attached to components of only the final-stage delay cell Dn.
Delay cell Dn includes: a current source transistor MC
1
having a driving current thereof controlled in accordance with the bias voltage V
1
; an insulated gate field effect transistor (referred to as an MOS transistor) M
5
of a p channel type connected between the current source transistor MC
1
and an output node, for receiving an output signal of the delay cell of a preceding stage at a gate thereof; an n-channel MOS transistor M
6
; and a current source transistor MC
2
connected between MOS transistor M
6
and the ground node, for receiving the bias voltage V
2
at a gate thereof signal of the previous-stage delay cell. Current source transistor MC
2
is coupled between MOS transistor M
6
and a ground node, and the gate of transistor MC
2
receives bias voltage V
2
.
Current source transistor MC
1
is formed of a p-MOS transistor. Current source transistor MC
2
is formed of an n-MOS transistor. Each of delay cells D
1
to Dn is formed of a CMOS inverter having the driving current set current source transistors MC
1
and MC
2
.
When the level of the bias voltage V
1
rises, and the level of the bias voltage V
2
decreases, the conductance of each of the current source transistors MC
1
and MC
2
are reduced, and the amount of the drive current thereof is reduced accordingly. Responsively, the operation speeds of delay cells D
1
to Dn are reduced. Accordingly, the oscillation cycle of oscillation circuit O is increased, and the oscillation frequency thereof is reduced.
When the level of bias voltage V
1
lowers and the level of the bias voltage V
2
increases, the conductances of current source transistors MC
1
and MC
2
increase, and the amount of the drive current thereof increases. Responsively, the operation currents of the respective delay cells D
1
to Dn increase, to increase the operation speeds thereof, and the oscillation cycle of oscillation circuit O decreased to increase the frequency of recovered clock signal CO.
The oscillation cycle of oscillation circuit O is controlled through bias voltages V
1
and V
2
in accordance with the phase difference between reference clock signal C and recovered clock signal CO, to synchronize in phase the reference clock signal C with the recovered clock signal CO. Thus, the recovered clock signal CO that tracks in frequency the reference clock signal C is generated.
FIG. 19
shows an example of the configuration of bias control circuit BK shown in FIG.
18
. Referring to
FIG. 19
, bias control circuit BK includes: an n-MOS transistor M
1
connected between a node AN and the ground node, and receiving the control voltage VC at a gate thereof; a p-channel MOS transistor M
2
connected between a power supply node and node AN, and having a gate connected to node AN; a p-MOS transistor M
3
connected between the power supply node and a node BN, and having a gate connected to node AN; and an n-MOS transistor M
4
connected between node BN and the ground node, and having a gate connected to node BN.
MOS transistors M
2
and M
3
form a current mirror circuit, in which a mirror current of the current flowing through MOS transistor M
2
flows through MOS transistor M
3
. That is, when MOS transistors M
2
and M
3
are the same in size (ratio of the channel width to the channel length) with each other, the currents of the same magnitude flow through MOS transistors M
2
and M
3
.
Control voltage VC is supplied from charge pump/low pass filter CPLP shown in FIG.
18
.
When the level of control voltage VC rises, the conductance of MOS transistor M
1
increases, and the current flowing through MOS transistor M
1
increases. The current is supplied to MOS transistor M
1
from MOS transistor M
2
, the amount of the current flowing via MOS transistor M
2
is thereby increased, and the current flowing via MOS transistor M
3
is increased accordingly. Since MOS transistor M
2
has the gate and drain thereof coupled together, and has the supply current thereof increased, the voltage level of node AN lowers. On the other hand, MOS transistor M
4
has the gate and drain thereof coupled to node BN, and has to discharge the current supplied from MOS transistor M
3
. Accordingly, the voltage level of node BN rises.
Specifically, when control voltage VC increases, the level of bias voltage V
1
lowers, while the level of bias voltage V
2
rises, conversely. These bias voltages V
1
and V
2
are supplied to the gates of current source transistors MC
1
and MC
2
, respectively. Thus, in oscillation circuit O, the operation currents of delay cells D
1
to Dn increase, and the operation speeds thereof increase accordingly. Consequently, the oscillation cycle of oscillation circuit O is decreased, and the frequency of recovered clock signal CO is increased.
When the level of control voltage VC lowers, the

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