Clock generator for a microprocessor having a delay equalization

Details Clock generator for a microprocessor having a delay equalization Clock generator for a microprocessor having a delay equalization

1996-10-02

1998-10-13

Heckler, Thomas M.

G06F 104

Patent

active

058225730

ABSTRACT:
A clock generator of the present invention comprises

REFERENCES:
patent: 5359727 (1994-10-01), Kurita et al.
patent: 5426772 (1995-06-01), Brady
patent: 5446867 (1995-08-01), Young et al.
I.A. Young, et al.,"A PLL Clock Generator With 5 to 110 MHz of Lock Range for Microprocessors", IEEE Journal of Solid-State Circuits, vol. 27, No. 11, Nov. 1992, pp. 1599-1607.

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