Clock generator circuit with low current frequency divider

Details Clock generator circuit with low current frequency divider Clock generator circuit with low current frequency divider

1994-01-27

1995-11-21

Lee, Benny

Oscillators

Combined with particular output coupling network

331116FE, 331158, 326 93, 326 96, 327544, 327291, 327115, 327176, 377126, H03B 530, H03B 536

Patent

active

054691168

ABSTRACT:
A clock generator circuit for producing a clock signal while drawing reduced current drain is disclosed. The clock generator circuit includes a crystal oscillator which produces a periodic signal having a relatively small voltage swing, controlled by one or more reference voltages; the reference voltages are preferably produced by a sub-threshold biased voltage reference circuit. The small signal output of the crystal oscillator is applied to the first of a series of frequency divider stages, prior to amplification by a level shift circuit. Each divider stage includes a current switch which switches the current drawn through current divider legs to produce output signals to latches in the divider stage. Each divider stage also includes one or more current source switched latches, each controlled by current sources that are switched by the current switch. As a result, each divider stage divides the frequency of the oscillator output signal without requiring amplification of the signal, thus reducing the active current. The output of the last divider stage is applied to a level shift circuit to provide the large voltage swing clock signal.

REFERENCES:
patent: 3956880 (1976-05-01), O'Connor
patent: 3999368 (1976-12-01), Yoshida
patent: 4094137 (1978-06-01), Morokawa
patent: 4389728 (1983-06-01), Tsuyuki
patent: 4591808 (1986-05-01), Lucas et al.
patent: 4656649 (1987-04-01), Takahashi
patent: 5065415 (1991-11-01), Yamashita
patent: 5172400 (1992-12-01), Maemura

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