Clock generator circuit providing reduced current consumption

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307480, 328 63, 328 72, 328120, 377 78, 377104, H03K 700, H03K 1700

Patent

active

051209888

ABSTRACT:
A clock generator contained in an integrated circuit has an input terminal, a first output terminal, and a second output terminal. When the input terminal of this clock generator receives a basic clock signal supplied by an external integrated circuit, the first output terminal outputs a first clock signal in response to the basic clock signal, and the second output terminal outputs a second clock signal which is an inverted clock signal of the first clock signal in response to the basic clock signal. When the input terminal receives a constant level signal supplied by the external integrated circuit, the first output terminal and the second output terminal output respectively the same constant level signal to thus provide reduced power consumption.

REFERENCES:
patent: 3720841 (1973-03-01), Suzuki
patent: 3737673 (1973-06-01), Suzuki
patent: 3971920 (1976-07-01), Johnson
patent: 4034301 (1977-07-01), Kashio
patent: 4341950 (1982-07-01), Kyles et al.
patent: 4472821 (1984-09-01), Mazin et al.
patent: 4794628 (1988-12-01), Sakamoto
patent: 4920282 (1990-04-01), Muraoka et al.

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