Clock generator circuit for use in a personal computer system

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

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Details

327144, 327160, 395550, H03B 1900, H03K 301

Patent

active

054324688

ABSTRACT:
A frequency dividing circuit/delay circuit is provided to generate a plurality of system clock signals according to the combination of frequency division and the delay based on a fast-speed basic clock signal to determine according to the address signal from a central processing unit (CPU) what the operating cycle of the slave is to select a system clock of optimum frequency or duty ratio for that slave. As a result, it becomes possible to shorten the time required for executing one cycle and, hence, to improve the performance of the whole personal computer system.

REFERENCES:
patent: 4191998 (1980-03-01), Carmody
patent: 4677499 (1987-06-01), Shirota et al.
patent: 4757264 (1988-07-01), Lee et al.
patent: 4845437 (1989-07-01), Mansur et al.
patent: 5086387 (1992-02-01), Arroyo et al.

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