Clock generator circuit

Details Clock generator circuit Clock generator circuit

2000-10-17

2001-12-11

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S099000

Reexamination Certificate

active

06329861

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a clock generator circuit and more specifically to a clock generator circuit which in use receives an input clock signal can provide a modified output clock signal.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention there is provided a clock generator circuit comprising a multiplexer, a clocked latch and pulse providing circuitry, said multiplexer having a first input node, a second input node, an output node and a clock terminal, said clocked latch having an input node, an output node and a clock terminal wherein said output node of said clocked latch is coupled to said first input node of said multiplexer and wherein said clocked latch is transparent when its clock terminal is at a first logic level, said pulse providing circuitry having an output connected to said second input node of said multiplexer and to said input node of said clocked latch, said pulse providing circuitry also having a clock terminal, wherein said clock generator circuit further has a clock node connected to said clock terminals of said multiplexer said latch and said pulse providing circuitry.
Preferably said clock node is connected to circuitry in use providing a two state clock signal.
Preferably said pulse providing circuitry comprises a finite state machine in use clocked by said clock signal.
In one embodiment said input node of said clocked latch and said second input of said multiplexer are connected in common and to a single output node of said pulse providing circuitry, whereby the multiplexer has an output which changes state at half the speed of said two state clock signal.
Advantageously, the output of said pulse providing circuitry comprise s a first circuit node in us e providing a first clock signal and a second output node in use providing to said second input node of said multiplexer and said second output node being connected to said input node of said clocked latch.
In a second embodiment the first logic signal is 0 in a first cycle, 1 in a second cycle and 0 in a third cycle and the second logic signal is in said first cycle 1, in said second cycle 1 and in said third cycle 0 whereby an output node of the multiplexer changes state at one third the rate of the two state clock signal.
In a third embodiment the first logic signal is, in a first cycle 1, in a second cycle 0 and in a third cycle 0 and the second logic signal is in the first cycle 0, in the second cycle 1 and in the third cycle 0 whereby the multiplexer output changes state every 1.5 state changes of the clock signal.


REFERENCES:
patent: 5390190 (1995-02-01), Nanda et al.
patent: 5604452 (1997-02-01), Huang
patent: 5794021 (1998-08-01), Hewitt
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patent: 6043692 (2000-03-01), Linoff
patent: 4034550-A1 (1991-02-01), None
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Patent Abstracts of Japan vol. 010, No. 082 (E-392), Apr. 2, 1986 & JP 60 227520 A (Matsushita Denki Sangyo KK) Nov. 12, 1985.
Patent Abstracts of Japan vol. 014, No. 229 (E-0928), May 15, 1990 & JP 02 058921 A (Nippon Telegr & Teleph Corp.) Feb. 28, 1990.
Patent Abstracts of Japan vol. 1996, No. 02, Feb. 29, 1996 & JP 07 273642 A (NEC Corp.) Oct. 20, 1995.

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