Clock generator and synchronizing method

Details Clock generator and synchronizing method Clock generator and synchronizing method

1999-06-29

2001-01-30

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S003000, C327S005000, C327S007000, C327S156000

Reexamination Certificate

active

06181175

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a clock generator having a tunable oscillator and a phase comparator, and to a method of generating a clock signal synchronized with an input signal by comparing the phase of a tunable oscillator with the phase of the signal input.
Network elements of a synchronous digital communications network such as an SDH (synchronous digital hierarchy) or SONET (synchronous optical network) system must be synchronized with a central reference clock which is derived from received message signals. To derive the reference clock signal and perform clock filtering, clock generators are used in each network element of the network. Such a clock generator contains a digital phase-locked loop (PLL), which is locked to an input signal and provides an output signal having the same frequency as the input signal on a long-term basis. A phase-locked loop comprises a tunable oscillator and a phase comparator which compares the input signal with the output signal of the oscillator and provides a resultant output value which is used as a correction signal for tuning the oscillator.
Each interruption of the input signal causes a phase transient in the output signal depending on the control time constant of the PLL. As a result, the average frequency of the output signal is corrupted, particularly in case of frequent short-time interruptions of the input signal. This effect is particularly pronounced in PLLs with edge-triggered phase comparators.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a clock generator which is insensitive to interruptions of the input signal. Another object of the invention is to provide a method of synchronizing a clock generator whereby no undesired phase transients are caused in the output signal by interruptions or disturbances of the input signal.
These objects and additional advantages features are attained by the present invention.
One advantage of the invention is that the effect of disturbances and interruptions of the input signal on the output signal is minimized. A further, particular advantage is that even frequent interruptions for fractions of a clock cycle do not result in phase transients in the output signal. This makes it possible to use even a disturbed signal as an input signal for synchronization.


REFERENCES:
patent: 3872455 (1975-03-01), Fuller et al.
patent: 4567448 (1986-01-01), Ikeda
patent: 4568881 (1986-02-01), Kostrov
patent: 4855683 (1989-08-01), Troudet et al.
patent: 5552726 (1996-09-01), Wichman et al.
patent: 40 24 239 C1 (1991-10-01), None
patent: 42 42 807 C1 (1994-03-01), None
patent: 195 23 186 A1 (1997-01-01), None
patent: 0 043 407 A2 (1982-01-01), None
patent: 0 567 990 A1 (1993-11-01), None
patent: 0 604 188 A2 (1994-06-01), None
patent: 0 715 412 A1 (1996-06-01), None

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