Clock generator and related biasing circuit

Details Clock generator and related biasing circuit Clock generator and related biasing circuit

2006-12-26

2006-12-26

Chang, Joseph (Department: 2817)

Oscillators

With particular source of power or bias voltage

C331S186000, C331S057000

Reexamination Certificate

active

07154352

ABSTRACT:
A clock generator capable of providing reduced low-frequency jitter clock signals without utilization of a crystal oscillator is introduced. The present invention clock generator utilizes a diode in related biasing circuit such that the generated control current to a current control oscillator is stable and clear due to the low flicker noise and low thermal noise of the voltage across the diode. The cost of PLL systems utilizing the present invention clock generator instead of a crystal oscillator is decreased. The adopted biasing circuit is introduced as well.

REFERENCES:
patent: 6803833 (2004-10-01), Yen et al.
patent: 2004/0245975 (2004-12-01), Tran et al.

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