Clock generator and delay stage

Details Clock generator and delay stage Clock generator and delay stage

1975-12-29

1977-12-06

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307208, 307246, 307269, 307270, 307DIG4, H03K 513, H03K 112, H03K 1908

Patent

active

040619338

ABSTRACT:
A clock generator for an MOSFET integrated circuit having a plurality of cascaded delay stages is disclosed. Each delay stage includes a bootstrap inverter having first and second transistors connected in series between the drain supply voltage and a source supply voltage, thus forming a first node between the transistors. The first node is capacitively coupled to a bootstrap node which is connected to the gate of the first transistor. The bootstrap node is also coupled through the channel of a third transistor to an input. The gate of the third transistor forms a third node. Circuit means are provided for precharging the third node and then isolating the third node while an input signal is applied through the third transistor to the bootstrap node so that the third node is also bootstrapped up to permit rapid charging of the bootstrap node to the full voltage of the input signal. The second transistor is held on by a precharge signal so that the first node is held low until the bootstrap node has been charged to the input voltage. Then both the third node and the gate of the second transistor are discharged to turn the second and third transistors off, thus permitting the bootstrap node to go rapidly above the drain supply voltage. The bootstrap node may be used directly as output, or can drive the gate of an output transistor so as to produce a very rapidly rising output which quickly reaches the full drain supply voltage. Circuit means is also provided to discharge the third node to disable the output before an input signal occurs. Since the third node is automatically discharged after receiving an input, the input may subsequently be changed without changing the output. Circuit means is also provided to selectively discharge the bootstrap node to isolate the output after it has achieved maximum voltage, so that the output can be capacitively boosted above the drain supply voltage. A circuit is also provided to reset the output to zero volts in conjunction with isolation of the output. A clock generator employing the various functions of a plurality of cascaded delay stages is also disclosed to demonstrate the capabilities of producing a series of clock pulses which go to V.sub.DD in timed sequence in response to input signal, of producing a voltage substantially above V.sub.DD, and of producing a pulse of predetermined duration.

REFERENCES:
patent: 3641366 (1972-02-01), Fujimoto
patent: 3641370 (1972-02-01), Heimbigner
patent: 3660684 (1972-05-01), Padgett et al.
patent: 3898479 (1975-08-01), Proebsting
patent: 3906464 (1975-09-01), Lattin
patent: 3932773 (1976-01-01), Luscher et al.
patent: 3937983 (1976-02-01), Reed

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