Clock generator and clock generating method using delay...

Details Clock generator and clock generating method using delay... Clock generator and clock generating method using delay...

2007-03-15

2008-10-14

Mis, David (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

With reference oscillator or source

C331S00100A, C331S016000, C331S025000, C327S158000

Reexamination Certificate

active

07436265

ABSTRACT:
Embodiments of a clock generator and a clock generating method can use a delay locked loop (DLL). In one embodiment, a clock generator can include a first oscillator to generate a first clock signal having a frequency corresponding to a control signal, a delay locked loop to generate a second clock signal having a frequency higher than that of the first clock signal, a frequency divider to receive the second clock signal to generate a third clock signal having a frequency lower than that of the second clock signal, a second oscillator to generate a fourth clock signal and a phase frequency detector to generate the control signal corresponding to a phase difference and/or a frequency difference between the third clock signal and the fourth clock signal.

REFERENCES:
patent: 6943609 (2005-09-01), Zampetti et al.
patent: 7102403 (2006-09-01), Wang
patent: 2004/0257124 (2004-12-01), Araki et al.

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