Clock generator and clock duty cycle correction method

Details Clock generator and clock duty cycle correction method Clock generator and clock duty cycle correction method

2008-05-06

2008-05-06

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Rectangular or pulse waveform width control

C327S172000, C327S176000

Reexamination Certificate

active

11323581

ABSTRACT:
A clock duty cycle correction (DCC) circuit for correcting a clock duty cycle of an external clock includes a phase comparator for comparing a phase of a rising clock with that of a falling clock to thereby output comparing signal; a DCC controller for outputting a DCC enable signal and a weight selection signal in response to the comparing signal and a first and a second lock state signal; a DCC mixing block for blending the rising clock and the falling clock in response to the DCC enable signal and the weight selection signal to thereby generate a rising and a falling pre-clock signals; and a clock selector for selectively output the rising and the falling pre-clock signals in response to the weight selection signal.

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