Clock generator

Details Clock generator Clock generator

1994-02-23

1995-12-05

Coleman, Eric

Boots, shoes, and leggings

364270, 3642702, 3642715, 3642591, 364DIG1, 395800, G06F 104

Patent

active

054737680

ABSTRACT:
A selector 11 selects one of a plurality of reference clock signals based upon a selection signal. A hardware reset signal 103 is delayed by a predetermined time. The selection signal is sent to the selector responsive to a set signal. The sending of the selection signal is stopped responsive to the delayed hardware reset signal. The set signal is delayed by a predetermined time. A first flip-flop 13 is set in response to the hardware reset signal or a software reset signal, is supplied with the delayed set signal as a count input, and is supplied with low level as a data input. A second flip-flop 16 receives a logic AND signal of an output signal from the selector 11 and the hardware reset signal as a count input and receives a logic OR signal of the output of the first flip-flop 13 and an inverted output of the second flip-flop 16 as a count signal, and generates a clock output.

REFERENCES:
patent: 4560939 (1985-12-01), DeKarske et al.
patent: 4669042 (1987-05-01), Henderson
patent: 5118975 (1992-06-01), Hillis
patent: 5369640 (1994-11-01), Watson

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