Clock generator

Details Clock generator Clock generator

1998-05-05

2000-12-05

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

327158, 327159, H03K 513

Patent

active

061572268

ABSTRACT:
In a multiplying circuit for providing a pulsed output clock signal have a frequency that is a multiple of a pulsed input clock signal, a delay of a digital delay line is initialized by initializing a counter when an external reset signal is input and when the number of pulses of the output clock signal from the clock generator is smaller than a predetermined multiplier. The delay of the digital delay line is set to a minimum value immediately following the initialization and then increased gradually in order to output the desired output clock signal.

REFERENCES:
patent: 4691170 (1987-09-01), Riley
patent: 5461332 (1995-10-01), Mirov et al.
patent: 5687202 (1997-11-01), Eitrheim
patent: 5771264 (1998-06-01), Lane
Combes, Michael, et al. "A Portable Clock Multiplier Generator Using Digital CMOS Standard Cells." IEEE Journal of Solid-State Circuits 31.7 (1996): 958-965.
Efendovich, Avner, et al. "Multifrequency Zero-Jitter Delay-Locked Loop." IEEE Journal of Solid-State Circuits 1.29 (1994): 67-70.

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