Clock generation system

Details Clock generation system Clock generation system

2006-08-01

2006-08-01

Pascal, Robert (Department: 2817)

Oscillators

Plural oscillators

Cascade or tandem connected

C331S002000, C331S046000, C377S048000

Reexamination Certificate

active

07084712

ABSTRACT:
A frequency-divided reference frequency clock is provided as a reference input to a phase comparator. An oscillation frequency signal of a controllable oscillator, having a frequency associated with another reference frequency clock, is frequency divided by a frequency division factor switching type comparison-input frequency division circuit. The resultant frequency-divided clock is provided as a comparison input to the phase comparator. The frequency division factor of the comparison-input frequency division circuit is switched from one to another based on a frequency division factor control signal to generate an oscillation frequency signal having a predetermined frequency ratio relative to another reference frequency clock. Thus, three reference frequency clocks of 27 MHz, 33.8688 MHz, and 36.864 MHz in accord with the MPEG format are obtained with a sufficient S/N ratio.

REFERENCES:
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patent: 6828863 (2004-12-01), Itkin et al.
patent: 2001/0008384 (2001-07-01), Ku
patent: 2004/0232995 (2004-11-01), Thomsen et al.

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