Clock generation network for level sensitive logic system

Details Clock generation network for level sensitive logic system Clock generation network for level sensitive logic system

1976-06-30

1977-12-13

Malzahn, David H.

Boots, shoes, and leggings

328 62, 364200, G06F 104

Patent

active

040630781

ABSTRACT:
Disclosed is an improved clock generation network. The improved clock generation network is particularly adapted to, and has particular utility when employed in a Level Sensitive Logic System generally of the type disclosed in U.S. Pat. No. 3,783,254, of common assignee.
The disclosed clock generation network also has particular utility in a Level Sensitive Embedded Array Logic System of the type disclosed in U.S. patent application Ser. No. 701,052, filed June 30, 1976, by Messrs. E. B. Eichelberger, E. I. Muehldorf, R. G. Walther and T. W. Williams and of common assignee.

REFERENCES:
patent: 3764992 (1973-10-01), Milne
patent: 3787817 (1974-01-01), Goldberg
patent: 3983538 (1976-09-01), Jones
J. E. Elliott et al. "Array Logic Processing" IBM Tech. Disclosure Bulletin vol. 16 No. 2 July 1973 pp. 586-587.

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