Computer graphics processing and selective visual display system – Display driving control circuitry – Display power source
Reexamination Certificate
1998-11-13
2001-10-30
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Display driving control circuitry
Display power source
C345S003100, C345S099000, C345S204000, C348S536000, C348S537000
Reexamination Certificate
active
06310618
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to digital graphics systems. More specifically, the present invention relates to methods and circuits for sampling analog video signals for digital display systems.
2. Discussion of Related Art
Analog video displays such as cathode ray tubes (CRTs) dominate the video display market. Thus, most electronic devices that require video displays, such as computers and digital video disk players, output analog video signals. As is well known in the art, an analog video display sequentially reproduces a large number of still images to give the illusion of full motion video. Each still image is known as a frame. For television, 60 frames are displayed in one second. For computer applications, the number of frames per seconds is variable with typical values ranging from 56 to 100 frames per seconds.
FIG.
1
(
a
) illustrates a typical analog video display
100
. Analog video display
100
comprises a raster scan unit
110
and a screen
120
. Raster scan unit
110
generates an electron beam
111
in accordance with an analog video signal VS, and directs electron beam
111
against screen
120
in the form of sequentially-produced horizontal scanlines
101
-
109
, which collectively form one frame. Screen
120
is provided with a phosphorescent material that is illuminated in accordance with the video signal VS transmitted in electron beam
111
to produce contrasting bright and dark regions that create an image, such as the diamond shape shown in FIG.
1
(
a
). After drawing each scanline
101
-
108
, raster scan unit
110
performs a horizontal flyback
130
to the left side of screen
120
before beginning a subsequent scanline. Similarly, after drawing the last scanline
109
of each frame, raster scan unit
110
performs a vertical flyback
131
to the top left corner of screen
120
before beginning a subsequent frame. To avoid generating an unwanted flyback traces (lines) on screen
120
during horizontal flyback
130
, video signal
130
includes a horizontal blanking pulse that turn off electron beam
111
during horizontal flyback
130
. Similarly, during vertical flyback
135
, video signal VS includes a vertical blanking pulse that turns off electron beam
111
during vertical flyback
135
.
FIG.
1
(
b
) illustrates a typical analog video signal VS for analog video display
100
. Video signal VS is accompanied by a horizontal synchronization signal HSYNCH and a vertical synchronization signal VSYNCH (not shown). Vertical synchronization signal VSYNCH contains vertical synch marks to indicate the beginning of each new frame. Typically, vertical synchronization signal VSYNCH is logic high and each vertical synch mark is a logic low pulse. Horizontal synchronization signal HSYNCH contains horizontal synch marks (logic low pulses)
133
,
134
, and
135
to indicate the beginning of data for a new scanline. Specifically, horizontal synch mark
133
indicates video signal VS contains data for scanline
103
; horizontal synch mark
134
indicates video signal VS now contains data for scanline
104
; and horizontal synch mark
135
indicates video signal VS now contains data for scanline
105
.
Video signal VS comprises data portions
112
,
113
,
114
, and
115
that correspond to scanlines
102
,
103
,
104
, and
105
, respectively. Video signal VS also comprises horizontal blanking pulses
123
,
124
and
125
, each of which is located between two data portions. As explained above, horizontal blanking pulses
123
,
124
, and
125
prevent the electron beam from drawing unwanted flyback traces on analog video display
100
. Each horizontal blanking pulse comprises a front porch FP, which precedes a horizontal synch mark, and a back porch BP which follows the horizontal synch mark. Thus, the actual video data for each row in video signal VS lies between the back porch of a first horizontal blanking pulse and the front porch of the next horizontal blanking pulse.
Digital video display units, such as liquid crystal displays (LCDs), are becoming competitive with analog video displays. Typically, digital video display units are much thinner and lighter than comparable analog video displays. Thus, for many video display functions, digital video displays are preferable to analog video displays. For example, a 19 inch (measured diagonally) analog video display, which has a 17 inch viewable area, may have a thickness of 19 inches and weigh 80 pounds. However, a 17 inch digital video display, which is equivalent to a 19 inch analog video display, may be only 4 inches thick and weigh less than 15 lbs. However, most computer systems are designed for use with analog video displays. Most computer systems output analog video signals, such as video signal VS and horizontal synchronization signal HSYNCH. Thus, the analog video signal provided by a computer must be converted into a format compatible with digital display systems.
FIG.
1
(
c
) illustrates a typical digital display
150
. Digital display
150
comprises a grid of picture elements (“pixels”) divided into rows
151
-
159
and columns
161
-
174
. Each data portion (e.g. data portions
112
,
113
,
114
, and
115
) is treated as one row of a digital display. Each data portion is also divided into smaller portions and digitized to form pixel data that is transmitted to its designated pixel using row driver
180
and column driver
190
. For most computer applications, the number of columns can be determined by the vertical resolution, which is equal to the number of rows. For example, common computer display formats include 640 columns by 480 rows (640×480), 800 columns by 600 rows (800×600), 1024 columns by 768 rows (1024×768), and 1280 columns by 1024 rows (1280×768). If video signal VS (FIG.
1
(
b
)) contains 480 rows, then data portion
114
is divided into 640 smaller portions, which are individually digitized to form 640 pixel data for pixels of one row. Typically, the digitized image is stored in a frame buffer, which is used to drive row driver
180
and column driver
190
. The actual physical digital display unit may contain thousands of pixels, thus the digital image stored in the frame buffer must be scaled accordingly before being displayed on the digital display.
To create a digital display from an analog video signal, the analog video signal must be digitized at precise locations to form the pixels of a digital display. Typically, a sampling clock signal is used to digitize video signal VS. However, the sampling clock signal must have a frequency and phase such that the sampling clock has the same number of periods during a data portion of video signal VS as the number of pixels to be sampled in that data portion. Creation of the sampling clock signal is complicated because the size of the front porch and back porch of a video signal may differ from computer to computer. Furthermore, different display resolutions on the same computer may also use differently sized front porches and back porches. Hence, there is a need for a method or circuit to generate a sampling clock signal that can be used to convert analog video signals into digital display data.
SUMMARY
The present invention generates a precisely tuned sampling clock signal, which can be used to convert analog video signals into pixels for digital displays. In accordance with one embodiment of the present invention, a mode detector determines a target pixel value that is equal to the desired number of pixels in a data portion of the video signal. A clock divider receives the horizontal synchronization signal of the video signal and generates a sampling clock signal using an initial divisor supplied by a divisor calculator. A counter measures a measured pixel value, which is equal to the number of pixels that would be sampled using the current sampling clock signal. The divisor calculator calculates a first divisor so that the measured pixel value will equal the target pixel value and transmits the first divisor to the clock divider. The clock divider
Kau Chin-Cheng
Zhang Biao
Bever Hoffman & Harms LLP
Kovalick Vincent E.
Mao Edward S.
Shalwala Bipin
SmartASIC, Inc.
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