Clock generation circuit having PLL circuit

Details Clock generation circuit having PLL circuit Clock generation circuit having PLL circuit

2001-04-02

2004-09-21

Shalwala, Bipin (Department: 2673)

Computer graphics processing and selective visual display system

Data responsive crt display control

Data responsive deflection control

C345S011000, C345S012000, C348S540000, C348S541000, C348S829000

Reexamination Certificate

active

06795043

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a clock generation circuit mounted on an image display device such as a display monitor or a television receiver.
2. Description of the Background Art
In a CRT (cathode ray tube), usually, there is a distortion in an image, depending on the overall shape of a Braun tube (cathode ray tube). Then, the distortion of the image is corrected by generating a distortion correction waveform. Further, because of variation in characteristics of parts, a horizontal position adjustment of screen is performed for each CRT in accordance with the characteristics of CRTs. The image distortion correction and the horizontal position adjustment of screen have been performed by using an analog circuit, but a desired operation with high accuracy cannot be necessarily obtained. A method to solve this situation is an image distortion correction and a horizontal position adjustment of screen using a digital signal.
FIG. 6
is a block diagram showing an overall constitution of a clock generation circuit in the background art which is proposed to perform the horizontal position adjustment and the image distortion correction using a digital signal. The clock generation circuit of
FIG. 6
comprises two PLL circuits for generating clocks locked with received reference signals. This clock generation circuit is disclosed in, e.g., Japanese Patent Application Laid Open Gazette No. 2000-172213.
In
FIG. 6
, a first PLL circuit is constituted of a first phase comparator
1
P (hereinafter, referred to as PC
1
P), a first low-pass filter
2
P (hereinafter, referred to as LPF
2
P), a first voltage controlled oscillator
3
P (hereinafter, referred to as VCO
3
P) and a first (1/N) variable divider
4
P (hereinafter, referred to as (1/N) divider
4
P).
On the other hand, a second PLL circuit is constituted of a second phase comparator
7
P (hereinafter, referred to as PC
7
P), a second low-pass filter
8
P (hereinafter, referred to as LPF
8
P), a second voltage controlled oscillator
9
P (hereinafter, referred to as VCO
9
P), a second (1/N) variable divider
10
P (hereinafter, referred to as (1/N) divider
10
P), a horizontal drive pulse generation unit
11
P and a deflection yoke
12
P which a CRT
13
P has.
Further, a digital delay unit
6
P plays an important part in the above-discussed horizontal position adjustment of screen and the image distortion correction.
Next, an operation of the clock generation circuit having the above constitution will be discussed.
First, the PC
1
P receives a horizontal synchronizing signal VHSYNC as a reference signal and compares the phases of the horizontal synchronizing signal VHSYNC and the other input signal VFP. The LPF
2
P on the next stage smoothes an output signal from the PC
1
P to generate a control voltage and outputs the control voltage to a control voltage receiving terminal of the VCO
3
P. In accordance with the control voltage, the VCO
3
P outputs a first clock signal CLK
1
P (hereinafter, referred to as clock CLK
1
P). The (1/N) divider
4
P divides the frequency of the clock CLK
1
P into (1/N) (N is any positive integer) and transmits the output signal to the PC
1
P as a feedback signal VFP. As a result, the phase of the feedback signal VFP is compared with the phase of the horizontal synchronizing signal VHSYNC by the PC
1
P. Thus, the first PLL circuit works with the horizontal synchronizing signal VHSYNC used as the reference signal.
Next, the clock CLK
1
P and a first reset signal VRS
1
P (hereinafter, referred to as reset signal VRS
1
P) which corresponds to the feedback signal VFP are transmitted from an output end of the first PLL circuit to an input end of the digital delay unit
6
P. The digital delay unit
6
P starts a count operation of the clock CLK
1
P in response to the input timing of the reset signal VRS
1
P and outputs a horizontal delay reference signal VHDR which is delayed in phase from the reset signal VRS
1
P at the timing of coincidence between the count value and a digital value (any one of a digital value for horizontal position adjustment, a digital value for PIN balance correction and a digital value for KEY balance correction) which is set in the digital delay unit
6
P before the reset signal VRS
1
P is inputted.
The horizontal delay reference signal VHDR is inputted to one input end of the PC
7
P as a reference signal of the second PLL circuit. The PC
7
P compares the phases of the horizontal delay reference signal VHDR and a signal VFBP received by the other input end and an output signal giving the phase difference is smoothed by the LPF
8
P to become a control voltage of the VCO
9
P. The VCO
9
P performs an oscillation operation in accordance with the control voltage to output a second clock signal CLK
2
P (hereinafter, referred to as clock CLK
2
P). The (1/N) divider
10
P divides the frequency of the clock CLK
2
P into 1/N (N is any positive integer) and transmits an output signal to the horizontal drive pulse generation unit
11
P as a second reset signal VRS
2
P (hereinafter, referred to as reset signal VRS
2
P). The horizontal drive pulse generation unit
11
P generates a horizontal drive pulse VHDP on the basis of the clock CLK
2
P and the reset signal VRS
2
P, to drive the deflection yoke
12
P. With this driving operation, in a horizontal output circuit (not shown) which the deflection yoke
12
P has, a flyback pulse of high energy is generated in a deflection coil (not shown) connected to a primary high-voltage winding of a flyback transformer (not shown) after a predetermined delay time passes from the input timing of the horizontal drive pulse VHDP. A step-down transformer circuit (not shown) having an input end connected to the one end of the deflection coil of the deflection yoke
12
P lowers the voltage of the flyback pulse and outputs the voltage-lowered flyback pulse VFBP (hereinafter, referred to simply as flyback pulse VFBP) to the PC
7
P. As a result, the PC
7
P compares the phases of the horizontal delay reference signal VHDR and the flyback pulse VFBP. Thus, the second PLL circuit works to generate the horizontal drive pulse VHDP with the horizontal delay reference signal VHDR used as the reference signal.
FIGS. 7A
to
7
E are timing charts of the signals at the time when the clock generation circuit of
FIG. 6
is brought into a steady state by the locking operation of the first and second PLL circuits.
Specifically,
FIG. 7A
shows the horizontal synchronizing signal VHSYNC which corresponds to the reference signal of the first PLL circuit, and the horizontal synchronizing signal VHSYNC is inputted to the PC
1
P.
FIG. 7B
shows the feedback signal VFP or the reset signal VRS
1
P of the first PLL circuit, and the feedback signal VFP is inputted to the PC
1
P and outputted to the digital delay unit
6
P at the same time. The first PLL circuit in the steady state keeps a condition where the phase difference between the horizontal synchronizing signal VHSYNC of FIG.
7
A and the feedback signal VFP of
FIG. 7B
is a time AD.
On the other hand,
FIG. 7C
shows the horizontal delay reference signal VHDR which corresponds to the reference signal of the second PLL circuit, and the horizontal delay reference signal VHDR is generated by the digital delay unit
6
P. A time period from an input timing (rise timing) of the reset signal VRS
1
P of
FIG. 7B
to the output timing (fall timing) of the horizontal delay reference signal VHDR of
FIG. 7C
is a delay time BD produced by the digital delay unit
6
P. Specifically, the digital delay unit
6
P generates the horizontal delay reference signal VHDR having a predetermined delay time BD in accordance with any one of the digital value for horizontal position adjustment, the digital value for PIN balance correction and the digital value for KEY balance correction which is set in the digital delay unit
6
P, and the image display device performs the horizontal position adjustment of screen and/or the image distortion correction by using the delay time BD.
FIG. 7D

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