Clock generation circuit having compensation for semiconductor m

Details Clock generation circuit having compensation for semiconductor m Clock generation circuit having compensation for semiconductor m

1995-03-30

1997-05-06

Yoo, Do Hyun

Static information storage and retrieval

Addressing

Sync/clocking

365191, 365194, G11C 1300

Patent

active

056277938

ABSTRACT:
A method and circuit for significantly reducing a delay added to a clock signal which clocks an output of a first circuit into an input of a second circuit in a semiconductor device. An output of a first circuit is connected to a data line. The first circuit is designed with elements having a selected set of design parameters, such as transistor dimensions and transistor orientation. A second circuit is connected to the data line and also receives a clock signal generated by a signal delay circuit. The signal delay circuit receives an output enable signal, and after a delay period, produces the clock signal in response to the output enable signal. At least a portion of the signal delay circuit utilizes elements having the selected set of design parameters utilized in the first circuit. Thus, as process variations affect the electrical properties and the speed of the transistors in the first circuit, the same process variations will proportionately affect the electrical properties and speed of transistors in the delay circuit. This automatically compensates for process-induced speed variations and eliminates the need for a time margin when providing a clock signal for clocking an output of a first circuit into the input of a second circuit.

REFERENCES:
patent: 4710902 (1987-12-01), Pelley, IV et al.
patent: 4727519 (1988-02-01), Morton et al.
patent: 4800304 (1989-01-01), Takeuchi
patent: 4841488 (1989-06-01), Sanada
patent: 4866675 (1989-09-01), Kawashira
patent: 5424985 (1995-06-01), McClure et al.

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