Clock generation circuit having a spread spectrum clocking...

Details Clock generation circuit having a spread spectrum clocking... Clock generation circuit having a spread spectrum clocking...

2006-11-30

2010-11-02

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S147000, C327S245000, C375S308000

Reexamination Certificate

active

07825707

ABSTRACT:
A multiphase clock generation circuit (111) for generating a multiphase clock signal, a phase subdivision unit (113) for shifting a phase of the multiphase clock signal output from the multiphase clock generation circuit (111), and a clock selection unit (114) for selecting one of clock signals output from the phase subdivision unit (113) are provided. A PLL circuit (120) for receiving an output from a frequency division circuit (115) is further provided. The phase shift carried out by the phase subdivision unit (113) and the selection of the clock signal carried out by the clock selection unit (114) are controlled by a frequency control unit (112) to switch SSC ON/OFF and to change the bandwidth of the PLL circuit (120).

REFERENCES:
patent: 2005/0135505 (2005-06-01), Ebuchi et al.
patent: 2005/1013550 (2005-06-01), Ebuchi et al.
patent: 2006/0076997 (2006-04-01), Ogasawara
patent: 2000-091911 (2000-03-01), None
patent: 2001-202153 (2001-07-01), None
patent: 2004-152361 (2004-05-01), None
patent: 2005-072939 (2005-03-01), None
patent: 2005-184488 (2005-07-01), None
“Serial ATA: High Speed Serialized AT Attachment” Revision 1.0, Aug. 29, 2001, Serial ATA.
Japanese Notice of Reasons for Rejection, with English Translation, issued in Japanese Patent Application No. 2007-553847, mailed Jan. 5, 2010.

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