Clock generation circuit generating internal clock of small...

Details Clock generation circuit generating internal clock of small... Clock generation circuit generating internal clock of small...

2001-02-28

2002-07-09

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S294000

Reexamination Certificate

active

06417715

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a clock generation circuit employed in a semiconductor memory device. More particularly, the present invention relates to a clock generation circuit generating an internal clock in synchronization with an external clock, and a semiconductor memory device including such a clock generation circuit.
2. Description of the Background Art
In a semiconductor device that operates in synchronization with an external clock such as an SDRAM (Synchronous Dynamic Random Access Memory), a clock generation circuit is provided in the semiconductor device. The internal circuit of the semiconductor device is generally controlled using an internal clock in synchronization with an external clock.
The circuit controlling the data input/output interface for the semiconductor device to send/receive data to/from an external source is under control using such an internal clock. Therefore, the data input/output timing is greatly influenced by the phase accuracy of the internal clock. The data output timing of an SDRAM will be described hereinafter as a typical example.
Referring to the timing chart of
FIG. 22
, a dock input circuit recognizes input of an external clock EXT.CLK at a timing (time t
0
) when the rising edge of external clock EXT.CLK exceeds the reference potential VREF. At time t
1
corresponding to an elapse of tD
1
from time t
0
, the clock input circuit renders internal clock CLKI active. This delay tD
1
corresponds to the phase delay generated in the clock input circuit.
A data output operation is initiated with internal clock CLKI as a trigger. At time t
2
corresponding to an elapse of tD
2
from time t
1
, output data DOUT is provided. Therefore, access time tAC defined starting from the excess of external clock EXT.CLK over reference potential VREF up to excess of output data DOUT over a potential VTT which is the output terminate level is the sum of delay tD
1
generated in the clock input circuit and delay tD
2
generated in the data output operation. In a general SDRAM, the specification value of access time tAC is limited to 3 nsec-6 nsec. Delay time tD
1
generated in the clock input terminal greatly affects access time tAC.
In accordance with the necessity of the semiconductor device operating at high frequency, the need arises to reduce the phase difference between the external clock edge and the input/output timing with respect to the semiconductor device. This is because the deviation in phase between the external clock edge and the data input/output timing is increased relatively with respect to the cycle of the external clock as the frequency of the external clock which is the reference in the operation of the semiconductor device becomes higher. The phase deviation will become too great to be neglected. In other words, the phase difference between the external clock edge and the operation timing of the input/output interface must be minimized in order to execute properly the command and data input/output with respect to the semiconductor device based on the external clock edge.
FIG. 23
is a timing chart of data output in a DDR-SDRAM (Double Data Rate-SDRAM).
Referring to
FIG. 23
, access time tAC corresponds to the period of time starting from time t
0
corresponding to the crossing point of the potential levels of external clock EXT.CLK and an inverted clock EXT./CLK up to time t
1
where output data DOUT exceeds the output terminate potential level VTT in a DDR-SDRAM.
In a DDR-SDRAM that inputs/outputs data in synchronization with both the rising and falling edges of an external clock, it is required that access time tAC takes a small value. The general specification of access time tAC is approximately ±0.75 nsec. In order to satisfy this access time specification, a clock generation circuit must be provided internally to control the phase difference between external clock EXT.CLK and internal clock CLKI, i.e. delay tD
1
occurring at the time of internal clock generation according to external clock EXT.CLK. A DLL (Delay Locked Loop) generally formed of a variable delay circuit and a phase comparator or a PLL (Phase Locked Loop) is generally applied as such a clock generation circuit.
A structure of a clock generation circuit using a DLL employed in a conventional DDR-SDRAM will be described hereinafter.
FIG. 24
is a block diagram showing a structure of a conventional clock generation circuit employing a DLL.
Referring to
FIG. 24
, the clock generation circuit includes a clock input circuit
125
, a variable delay circuit
130
, replica circuits
140
and
160
, a phase comparator
200
, and a delay control circuit
150
.
Clock input circuit
125
detects the crossing point of the potential levels of external clock EXT.CLK and inverted clock EXT./CLK forming complementary clocks to generate an internal clock CLK
1
. If the time required to generate internal clock CLK
1
in clock input circuit
125
is tD
1
, internal clock CLK
1
already lags in phase by delay tD
1
from the crossing point of the potential levels of the complementary clocks at this stage.
Variable delay circuit
130
further delays internal clock CLK
1
to generate an internal operation clock CLK
2
. Data output control circuit
50
operates in response to internal operation clock CLK
2
to provide data DOUT to a data input/output terminal EXT.DQ.
Assuming that the cycle of external clock EXT.CLK is tCLK and the time required from activation of internal operation clock CLK
2
up to the output of data DOUT is tD
2
, access time tAC can be set equal to external clock cycle tCLK by setting the delay time of variable delay circuit
130
to “tCLK−(tD
1
+tD
2
)” by delay control circuit
150
. In this case, access time tAC is equivalently 0 as to the data output interface when viewed from outside the semiconductor device. Data output will be executed at a timing in synchronization with the external clock edge.
Since the delay value of variable delay circuit
130
is set to the foregoing “tCLK−(tD
1
+tD
2
)”, internal operation clock CLK
2
is further delayed by two replica circuits
140
and
160
to be applied to phase comparator
200
as return clock RCLK. Replica circuit
140
functions to replicate the delay corresponding to delay amount tD
2
generated at data output control circuit
50
with respect to internal operation clock CLK
2
. Similarly, replica circuit
160
replicates delay corresponding to delay amount tD
1
generated at clock input circuit
125
with respect to the output of replica circuit
140
.
Phase comparator
200
compares the phases between return clock RCLK output from replica circuit
160
and internal clock CLK
1
of one succeeding cycle to generate a control signal UP/DOWN to increase/decrease the amount of delay of variable delay circuit
130
according to the phase difference.
Delay control circuit
150
generates a delay control signal CTRL according to control signals UP and DOWN to adjust the delay amount of variable delay circuit
130
. When the phases of internal clock CLK
1
and return clock RCLK match, delay control signal CTRL takes a certain fixed value, whereby the delay amount of variable delay circuit
130
is fixed. In this state, internal clock CLK
1
is in phase with return clock RCLK. This state is called “lock state” hereinafter.
Therefore, internal operation clock CLK
2
is ahead in phase of internal clock CLK
1
output from clock input terminal
125
by the delay amount applied at replica circuits
140
and
160
. When the sum of the delay amount of replica circuits
140
and
160
exactly matches (tD
2
+tD
1
), the delay value of variable delay circuit
130
becomes “tCLK−(tD
1
+tD
2
)”, so that access time tAC seems to be 0, as mentioned before.
FIG. 25
is a block diagram showing another structure of a clock generation circuit employed in a DDR-SDRAM.
Referring to
FIG. 25
, the clock generation circuit generates internal operation clocks FCLK
2
and BCLK
2
corresponding to both the rising and falling edges of exter

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