Clock generation circuit for multistandard serial digital video

Oscillators – Automatic frequency stabilization using a phase or frequency... – Afc with logic elements

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331 20, 331 25, 331179, 331DIG2, 358140, 358158, H03L 718

Patent

active

051111608

ABSTRACT:
A voltage controlled reference oscillator with a high Q and narrow tunability bandwidth produces an output oscillator frequency which is frequency divided by four alternative constants to produce four different clock frequencies for four different digital video standards, D1 component at 270 MHz, NTSC D2 composite at 143 MHz, PAL D2 composite at 177 MHz, and a proposed new composite video standard that is to operate at a 360 MHz clock rate. Automatic identification of which serial digital video is present is accomplished by having the clock generator produce a clock signal at the frequency required by one of the video formats while a phase lock loop attempts to lock onto the incoming signals at that frequency. If no lock occurs within a predetermined time interval, the clock generator is made to produce a clock signal at the frequency required by a different one of the video formats and the phase lock is attempted again. This is repeated until a lock is attained. Optionally, when a lock occurs, the video is tested for validity within the format that is consistent with the clock frequency that produced the lock.

REFERENCES:
patent: 4680555 (1987-07-01), Waldeck
patent: 4958228 (1990-09-01), Kutsuki
patent: 4962427 (1990-10-01), Lunn et al.
Digital Transmission Systems, by David R. Smith, 1985 Van Nostrand Reinhold Company, Sec. 4.2.

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