Clock generation circuit for a display controller having a fine

Details Clock generation circuit for a display controller having a fine Clock generation circuit for a display controller having a fine

1995-05-26

1998-10-13

Hjerpe, Richard A.

Computer graphics processing and selective visual display system

Plural physical display element control system

Display elements arranged in matrix

345213, G09G 336

Patent

active

058219102

ABSTRACT:
A clock generation circuit for a display controller includes an intermediate dot clock generation circuit which receives an input clock signal and in response thereto generates an intermediate dot clock signal having a plurality of dot clock pulses. A row pulse generation circuit is coupled to the intermediate dot clock generation circuit and counts the intermediate dot clock signal dot clock pulses and generates a row pulse after a predetermined number of dot clock pulses and a programmable offset time. The row pulse generation circuit also generates a final dot clock signal by masking the intermediate dot clock signal with the programmable offset time after the predetermined number of dot clock pulses. A method of adjusting a rate at which data is transferred to a display screen is also disclosed.

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