Clock generation circuit and semiconductor memory device...

Details Clock generation circuit and semiconductor memory device... Clock generation circuit and semiconductor memory device...

2005-11-22

2005-11-22

Mai, Son (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S193000

Reexamination Certificate

active

06967895

ABSTRACT:
In an internal clock control circuit (5) that receives a DQSEsignal whose timings have been controlled by a CLK signal received by a register (3) and a write CMD received by an enable signal control circuit (4), by a DQSin signal output from a first-stage input circuit2for a DQS signal, and the DQSEsignal, two NAND circuits constituting a flip flop circuit turn a p-channel transistor (Q) on when a signal waveform in the first cycle is input, and off when signal waveforms in the second or subsequent cycle.

REFERENCES:
patent: 6680869 (2004-01-01), Sonoda et al.
patent: 2003/0217225 (2003-11-01), Jang et al.
patent: 2000-114954 (2000-04-01), None
patent: 2001-126481 (2001-05-01), None

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