Clock generation circuit and semiconductor integrated circuit

Details Clock generation circuit and semiconductor integrated circuit Clock generation circuit and semiconductor integrated circuit

1999-07-23

2001-02-20

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S262000, C327S271000

Reexamination Certificate

active

06191632

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a clock generation circuit and a semiconductor integrated circuit and, more particularly, to a circuit construction for generating a clock (internal clock) having no phase error due to the location of the circuit in a semiconductor integrated circuit, in accordance with a clock (external clock) supplied from the outside of the semiconductor integrated circuit.
BACKGROUND OF THE INVENTION
Recently, in data transfer processing, a method of inputting/outputting data in synchronization with a clock is employed to realize high-speed data transfer.
Especially in a frequency region where a clock frequency exceeds 100 MHz, it is necessary to synchronize an external clock and an internal clock by using a feedback control system such as a PLL (Phase-Locked Loop) or a DLL (Delay-Locked Loop).
Further, also in a semiconductor integrated circuit such as an LSI (Large Scale Integrated circuit), there exists a skew (phase error between clocks) depending on the distance from a clock supply circuit.
In order to reduce the influence of skew, a conventional semiconductor integrated circuit is provided with driver circuits and DLL circuits which are located in several positions on a clock supply wiring inside the circuit.
Hereinafter, a brief description will be given of the conventional semiconductor integrated circuit. When a clock wiring driven by a clock generation circuit is long, the output impedance of a driver circuit win the clock generation circuit to the wiring load cannot be sufficiently reduced, whereby inclination of edges of a clock waveform increases, resulting in an increase in delay time of a clock in the clock wiring. In order to solve this problem, in the conventional semiconductor integrated circuit, driver circuits are inserted in several positions of the clock wiring to prevent the waveform from rounding, and a delay of the clock due to the driver circuits is canceled by using DLL circuits.
In the conventional semiconductor integrated circuit, since a delay caused by the driver circuits is canceled by the DLL circuits, a pulse having a waveform of steep edges can be transmitted as a clock. However, a delay of the clock caused by the resistance and capacitance of the wiring cannot be eliminated.
According to the existing LSI manufacturing process conditions, the time constant of a metal wiring having a width of 1 &mgr;m and a length of 1 cm is about 1 ns and, therefore, it is difficult to realize an LSI operating at several hundreds of MHz by using such metal wiring.
SUMMARY OF THE INVENTION
The present invention is made to solve the above-described problems and has for its object to provide a clock generation circuit which can generates internal clocks of the same phase regardless of positions in a semiconductor integrated circuit.
It is another object of the present invention to provide a semiconductor integrated circuit in which input data is latched by using the above-mentioned clock generation circuit.
Other objects and advantages of the invention will become apparent from the detailed description that follows. The detailed description and specific embodiments described are provided only for illustration since various additions and modifications within the scope of the invention will be apparent of those of skill in the art from the detailed description.
According to a first aspect of the present invention, there is provided a clock generation circuit comprising a clock wiring having opposed first and second ends, through which a clock is transmitted from the first end to the second end, and a plurality of clock phase adjustment circuits for generating internal clocks in accordance with the clock supplied from the clock wiring. Each of the clock phase adjustment circuits comprises a first-end side terminal and a second-end side terminal which are connected to a first-end side point and a second-end side point of the circuit, respectively, the points being positioned on both sides of a reference point of the clock wiring; delay means for delaying a clock supplied from one of the terminals and outputting an internal clock; and delay control means for performing feedback control on a delay of the clock in the delay means in accordance with the phase of the clock supplied from the other terminal so that the phase of the internal clock matches the phase of the clock at the reference point of the clock wiring. Therefore, internal clocks of the same phase are output from the respective clock phase adjustment circuits, and the internal clocks of the same phase can be supplied to everywhere in a semiconductor integrated circuit including the clock generation circuit. As the result, data can be stably latched by using the internal clocks in every position in the semiconductor integrated circuit.
According to a second aspect of the present invention, in the clock generation circuit of the first embodiment, the clock wiring is turned down at the reference point such that a portion of the wiring from the first end to the reference point and a portion of the wiring from the reference point to the second end are positioned in parallel with each other, and the distance from the first-end side point to the reference point of the clock wiring corresponding to each clock phase adjustment circuit is equal to the distance from the second-end side point to the reference point of the clock wiring corresponding to each clock phase adjustment circuit. Therefore, when the respective clock adjustment circuits are arranged along the clock wiring, the distances from the first-end side point and the second-end side point of the clock wiring to the first-end side terminal and the second-end side terminal of each clock phase adjustment circuit can be reduced. In addition, the distance from the first-end side point of the clock wiring to the first-end side terminal of the clock phase adjustment circuit can be approximately equal to the distance from the second-end side point of the clock wiring to the second-end side terminal of the clock phase adjustment circuit.
According to a third aspect of the present invention, in the clock generation circuit of the second aspect, the delay means delays the clock input to the first-end side terminal of the clock phase adjustment circuit to output the internal clock, and the delay control means performs feedback control on a delay of the clock in the delay means in accordance with the phase of the clock input to the second-end side terminal of the clock phase adjustment circuit so that the phase of the internal clock matches the phase of the clock at the reference point of the clock wiring. Therefore, the phase difference between the internal clock and the input clock applied to the input end (first end) of the clock wiring can be reduced.
According to a fourth aspect of the present invention, in the clock generation circuit of the third aspect, the clock phase adjustment circuit further comprises additional delay means for delaying the internal clock output from the delay means and outputting the delayed internal clock; phase comparison means for comparing the phase of the delayed internal clock with the phase of the clock input to the second-end side terminal of the clock phase adjustment circuit and outputting a phase comparison signal indicating the result of the comparison; and the delay control circuit performing feedback control in accordance with the phase comparison signal so that the delay in the delay means becomes equal to the delay in the additional delay means, and the phase of the internal clock matches the phase of the clock at the reference point of the clock wiring. Therefore, the delay means and the additional delay means can be implemented by the same delay circuit and, furthermore, the delays in the respective delay means are always constant, whereby delay control is simplified.
According to a fifth aspect of the present invention, in the clock generation circuit of the second aspect, the delay means delays the clock input to the second-end side terminal of the clock phase adjustment cir

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