Clock generation circuit

Details Clock generation circuit Clock generation circuit

2008-12-30

2010-10-12

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000

Reexamination Certificate

active

07812658

ABSTRACT:
A clock generation circuit, which includes a reference clock delay circuit including a number M of delay units connected in series, and configured to delay a reference clock by L cycles; and an oscillation circuit including a number N of delay units connected in series, and configured to generate an oscillation clock according to the following Equation,tOS=2⁢⁢N×DD=2⁢⁢N×L×tCLKMwhere each delay unit is configured to delay an input signal by a reference delay amount DD, tOS is a period of the oscillation clock, and tCLK is the reference clock.

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“A Low-Power Small-Area ±7.28-ps-Jitter 1-GHz DLL-Based Clock Generator”; Chulwoo Kim et al., IEEE, vol. 37, No. 11, Nov. 11, 2002.

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