Clock generation and distribution system for a memory controller

Details Clock generation and distribution system for a memory controller Clock generation and distribution system for a memory controller

1993-11-12

1995-12-26

Heckler, Thomas M.

Boots, shoes, and leggings

364DIG1, 3642711, 3642715, 3642384, G06F 1342

Patent

active

054796474

ABSTRACT:
A clock generation and distribution system for a memory controller in a computer system is described. The memory controller includes a CPU interface circuit-that interfaces with a microprocessor, a bus controller interface circuit that interfaces with a bus controller, and a main memory controller circuit coupled to a memory for controlling memory operations of the memory. The clock generation and distribution system includes a clock generation circuit for generating a first clock signal in accordance with an input clock signal. A delay circuit delays the first clock signal to be a delayed first clock signal. The delay circuit has a controllable delay. An electrical connection circuit external to the memory controller transfers the delayed first clock signal to the (1) the microprocessor, (2) the bus controller, (3) the CPU interface circuit, and (4) the bus controller interface circuit such that the CPU interface circuit is synchronized with the microprocessor and the bus controller interface circuit is synchronized with the bus controller by the delayed first clock signal. The electrical connection circuit generates a signal transfer delay to the delayed first clock signal. The delay circuit controls the controllable delay such that the delayed first clock signal with the signal transfer delay is also synchronized with the input clock signal.

REFERENCES:
patent: 5276858 (1994-01-01), Oak et al.
"82369 DRAM Controller," Intel Peripheral Components, pp. 1-522 through 1-700 (1993).

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