Clock generation and distribution in an emulation system

Details Clock generation and distribution in an emulation system Clock generation and distribution in an emulation system

2005-08-23

2005-08-23

Thomson, W (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Emulation

C703S025000, C703S027000, C703S028000, C703S019000

Reexamination Certificate

active

06934674

ABSTRACT:
A method and apparatus for clock generation and distribution in an emulation system is described. The present invention provides a method and apparatus for generating a derived clock signal with a circuit having a look up table. A counter circuit counts clock cycles and provides an index into the look up table. A frequency divider circuit may be used between the counter circuit and a base clock signal to provide an intermediate clock signal with a frequency that is less than the frequency of the base clock signal. In one embodiment, a selection circuit is provided to select between the base clock signal and an external clock signal.

REFERENCES:
patent: 4759014 (1988-07-01), Decker et al.
patent: 5036473 (1991-07-01), Butts et al.
patent: 5452239 (1995-09-01), Dai et al.
patent: 5491442 (1996-02-01), Mirov et al.
patent: 5623418 (1997-04-01), Rostoker et al.
patent: 5701441 (1997-12-01), Trimberger
patent: 5838956 (1998-11-01), Kawasaki et al.
patent: 5954787 (1999-09-01), Eun
patent: 6055489 (2000-04-01), Beatty et al.
patent: 6064247 (2000-05-01), Krakirian
patent: 6135648 (2000-10-01), Stefek et al.
patent: 6304125 (2001-10-01), Sutherland
patent: 6392496 (2002-05-01), Lee et al.
patent: 50-72549 (1975-06-01), None
patent: 56-68813 (1981-06-01), None
patent: 57-148231 (1982-09-01), None
patent: 57-185720 (1982-11-01), None
patent: 58-014227 (1983-01-01), None
patent: 58-175035 (1983-10-01), None
patent: 59-9765 (1984-01-01), None
patent: 59-085527 (1984-05-01), None
patent: 60-49421 (1985-03-01), None
patent: 61-133830 (1986-08-01), None
patent: 61-267812 (1986-11-01), None
patent: 62-194510 (1987-08-01), None
patent: 63-007016 (1988-01-01), None
patent: 63-44215 (1988-02-01), None
patent: 63-276915 (1988-11-01), None
patent: 64-46118 (1989-02-01), None
patent: 1-260518 (1989-10-01), None
patent: 2-209010 (1990-08-01), None
patent: 03-085012 (1991-04-01), None
patent: 3-248213 (1991-11-01), None
patent: 4-315209 (1992-11-01), None
patent: 06-282348 (1994-10-01), None
patent: 07-262037 (1995-12-01), None
Rahkonen, T.; Eksyma, H., “A 3-V programmable clock generator with a built-in phase interpolator,” Proceedings of the 1998 Midwest Symposium on Circuits and Systems, 1998, pp.: 488-491.
“Translation of Final Rejection of the Japanese Patent Office,” from counterpart Japanese Application No. 2001-500405, mailed Mar. 25, 2003 (2 pages).
“Translation of an Office Action of Japanese Patent Office,” from counterpart Japanese Application No. 2001-500405, 3 pgs., mailed Aug. 27, 2002.
XILINX, “The Programmable Gate Array Design Handbook,” First Edition, 1986, pp. i-A-10.
Mel Bazes, “An Interpolating Clock Synthesizer,” IEEE J. of Solid State Circuits, vol. 31, No. 9, pp. 1295-1301 (Sep. 1996).
International Search Report for PCT/US00/03261, issued Jun. 23, 2000.
Translation of Oct. 28, 2003 Office Action in Japanese application 2001-500405.

Affiliated with

Also associated with

Rating

Clock generation and distribution in an emulation system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock generation and distribution in an emulation system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock generation and distribution in an emulation system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3519939