Clock generation

Details Clock generation Clock generation

1993-02-25

1994-09-06

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370112, 307269, H04J 300

Patent

active

053454499

ABSTRACT:
In an integrated circuit, a multiplexor receives incoming data at a first rate and is controllable by a high rate clock signal to output that data serially at a second, higher rate. A processing device receives the data from the multiplexor at the higher rate and is controllable by a high rate clock signal to process that data. Clock generation circuitry receives a first clock signal at the first rate and produces the high rate signal for the processing device and the multiplexor. Clock generation circuitry includes sequentially connected delay devices, one connected to receive the first clock signal. Each delay device produces a trigger signal and an output signal a predetermined time after receiving the trigger signal from the previous delay device. A control circuit is common to the delay devices for controlling the predetermined time interval. An output circuit receives the output signals of the delay devices and produces the high rate clock signal.

REFERENCES:
patent: 3631464 (1971-12-01), Dahlberg
patent: 3995119 (1976-11-01), Pachynski, Jr.
patent: 4613775 (1986-09-01), Dick
patent: 4691124 (1987-09-01), Ledzius et al.
Bult et al. "A CMOS Analog Continuous-Time Delay Line with Adaptive Delay-Time Control" Journal of Solid State Circuits, vol. 23, No. 3 (Jun., 1988).
Brooktree Corporation specification sheet Bt459 Monolithic CMOS device, Rev. J., pp. 1 and 4 (prior to Jul., 1988).
Brooktree Corporation specification sheet Bt459 Monolithic CMOS device, Rev. B, pp. 1-4, and copyright notice page (1988).

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