Clock generation

Details Clock generation Clock generation

1990-06-22

1993-09-07

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

307269, H04J 300

Patent

active

052435970

ABSTRACT:
An integrated circuit including a multiplexor connected to receive incoming data at a first rate and controllable by a high rate clock signal to output that data serially at a second, higher rate; a processing device coupled to receive data output from the multiplexor at the higher rate and controllable by a high rate clock signal to process that data; and clock generation circuitry connected to receive a first clock signal at said first rate and operable to produce therefrom said high rate clock signal to be supplied to the processing device and to the multiplexor. There is also described clock generation circuitry including a plurality of sequentially connected delay devices, a first one of which is coupled to receive the first clock signal, each delay device being operable to produce a trigger signal and an output signal at a predetermined time after receiving a trigger signal from the previously connected delay device; control circuits common to the delay devices for controlling the predetermined time interval; and output circuits coupled to receive the output signals of the delay devices to produce therefrom the second clock signal.

REFERENCES:
patent: 3995119 (1976-11-01), Pachynski, Jr.
patent: 4613775 (1986-09-01), Dick
patent: 4691124 (1987-09-01), Ledzius et al.
Bult et al., "A CMOS Analog Continuous-Time Dealy Line with Adaptive Delay-Time Control", IEEE J. of Solid State Circuits, vol. 23, No. 3, pp. 759-761 (Jun. 1988).

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