Clock generating method and clock generating circuit

Pulse or digital communications – Spread spectrum

Reexamination Certificate

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Details

C375S376000, C375S152000, C331S010000, C331S011000, C331S017000, C327S156000

Reexamination Certificate

active

07580443

ABSTRACT:
In a clock generating circuit, while a PLL (Phase-Locked Loop) circuit and a modulator are employed, when a frequency dividing ratio of a feedback-purpose frequency divider in the PLL circuit is changed in accordance with modulation data produced based upon a modulation profile of the modulator to perform a frequency modulation so as to spread a spectrum, a turning point of the modulation profile is moved so as to disperse a degree of frequency, so that the spread spectrum is re-spread. Also, a clock generating circuit is constituted by a PLL circuit and a modulator, a multiple modulation profile generating circuit is provided in the modulator, and a turning point of a modulation profile is moved so as to disperse a degree of frequency, so that a spread spectrum is re-spread.

REFERENCES:
patent: 5488627 (1996-01-01), Hardin et al.
patent: 5659587 (1997-08-01), Knierim
patent: 6980581 (2005-12-01), Sha et al.
patent: 7015733 (2006-03-01), Giuroiu
patent: 2005/0008113 (2005-01-01), Kokubo et al.
patent: 2005/0134335 (2005-06-01), Loh
patent: 7-235862 (1995-09-01), None
patent: 2001-202153 (2001-07-01), None
patent: 2004-104655 (2004-04-01), None
K. Hardin et al., “Spread Spectrum Clock Generation for the Reduction of Radiated Emissions,” IEEE, 1994, pp. 227-231.
D. Kim et al., “A Spread Spectrum Clock Generation PLL with Dual-tone Modulation Profile,” 2005 Symposium on VLSI Circuits Digest of Technical Papers, 2005, pp. 96-99.

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