Clock generating circuit providing a boosted clock signal

Details Clock generating circuit providing a boosted clock signal Clock generating circuit providing a boosted clock signal

1983-06-09

1986-03-04

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307482, 307578, 307579, H03K 502

Patent

active

045742030

ABSTRACT:
A clock generating circuit includes a switch control circuit controlling a C-MOS circuit including first and second transistors having first and second conductivity types, respectively. Also included in the clock generating circuit is a bootstrap capacitor having a first end connected to the junction between the first and second transistors. The switch circuit includes a third transistor, having the first conductivity type, connected between the gate of the first transistor and the junction between the first and second transistors, and a fourth transistor, having the second conductivity type, connected between the gates of the first and second transistors. The gate of the second transistor is connected to receive an input clock signal and the gates of the third and fourth transistors are connected together to receive a delayed clock signal produced by delaying the input clock signal. The second end of the bootstrap capacitor is connected to receive a further delayed and inverted clock signal. When the delayed clock signal has a first value, the switching circuit connects the gates of the first and second transistors together and an output signal with a first level is produced at the junction of the first and second transistors. When the delayed clock signal reaches a second level, the switching circuit connnects the gate of the first transistor to the junction of the first and second transistors and the bootstrap capacitor boosts the output signal to a second level.

REFERENCES:
patent: 4061933 (1977-12-01), Schroeder et al.
patent: 4382194 (1983-05-01), Nakano et al.
patent: 4388538 (1983-06-01), Ikeda
IBM Technical Disclosure Bulletin, vol. 18, No. 2, Jul. 1975, New York, pp. 467-468, M. Cukier: "Push-Pull Circuit".

Affiliated with

Also associated with

Rating

Clock generating circuit providing a boosted clock signal does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock generating circuit providing a boosted clock signal, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock generating circuit providing a boosted clock signal will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1595566