Clock generating circuit, PLL circuit, semiconductor device, and

Details Clock generating circuit, PLL circuit, semiconductor device, and Clock generating circuit, PLL circuit, semiconductor device, and

1996-01-19

1998-09-01

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

327149, 327158, 327244, 327270, 327276, H03L 700

Patent

active

058015590

ABSTRACT:
A clock generating circuit includes a plurality of delay lines connected in cascade, each delay line including two switching elements for letting in or shutting out a clock, and a delay element connected to each of the switching elements. A PLL circuit and a semiconductor device both include the clock generating circuit. The number K of the delay units in each of the delay lines of the clock generating circuit is calculated from:

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A. Efendovich et al., "Multifrequency Zero-Jitter Delay-Locked Loop", IEEE Journal of Solid-State Circuits, vol. 29, No. 1, Jan. 1994, pp. 67-70.
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