Clock generating circuit having high resolution of delay time be

Details Clock generating circuit having high resolution of delay time be Clock generating circuit having high resolution of delay time be

1998-06-10

2000-05-30

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327153, 327299, 327276, H03K 5159

Patent

active

060695080

ABSTRACT:
A clock generating circuit synchronizes an internal clock signal with an external clock signal, and has a delay circuit implemented by a series of delay stages connected through pairs of signal transfer lines to one another; each of the delay stages has a series combination of a first charging circuit and a first discharging circuit connected between a positive power line and a ground line and a series combination of a second charging circuit and a second discharging circuit connected in parallel to the first series combination, and each pair of signal transfer lines is connected between the first series combination of one of the delay stage and the second series combination of the next delay series; a potential edge signal is propagated through charging/discharging operations toward a certain delay stage during a first time period equal to the pulse period of the external clock signal, and returns to the first delay stage so as to generate a one-shot pulse in the next pulse period; even if the pulse period fluctuates, the delay circuit changes the turning point of the potential edge signal, and makes the internal clock signal strictly synchronous with the external clock signal.

REFERENCES:
patent: 5699003 (1997-12-01), Saeki
patent: 5929682 (1999-07-01), Kazuya et al.
Yoshinori Okahima et al., "Digital Delay Locked Loop and Design Technique for High-Speed Synchronous Interface", IEICE Trans. Electron., vol. E79-C, No. 6, Jun. 1996, pp. 798-807.
Atsushi Hatakeyama et al., "A 256Mb SDRAM Using a Register-Controlled Digital DLL", 1997 IEEE International Solid-State Circuits Conference, Paper TP 4.5, 1997, pp. 72-73.
Jin-Man Han et al., "Skew Minimization Techniques for 256M-bit synchronous DRAM and beyond", 1996 Symposium on VLSI Circuits Digest of Technical Papers, 1996, pp. 192-193.
Toshio Yamada et al., "Capacitance coupled Bus with Negative Delay Circuit for High speed and Low Power (10GB/s<500mW) Synchronous DRAMs", 1996 Symp. on VLSI Circuits Dig. of Tech. Papers, 1996, pp. 112-113.
NEC 1996 Data Book: IC Memory Dynamic RAM 2, Oct. 1996, pp. 376-377.

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