Clock generating circuit generating a plurality of non-overlappi

Details Clock generating circuit generating a plurality of non-overlappi Clock generating circuit generating a plurality of non-overlappi

1994-11-30

1996-07-02

Cunningham, Terry

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Rectangular or pulse waveform width control

327176, 327118, 327235, 327251, 327299, H03K 3017

Patent

active

055326331

ABSTRACT:
A first basic clock supplied from outside is delayed by a first delay circuit to generate a second basic clock which is fed to a frequency divider to generate a group of multi-phase clocks, each of which has a clock width equal to an integer number multiple of the clock width of the second basic clock and has a phase delay sequentially by a value equal to an integer number multiple of the clock period of the second basic clock, wherein the (n-1)th multi-phase clock and a nth multi-phase clock neighboring to each other in the phase sequence, and the first basic clock, are fed to a delay generating circuit as inputs, which comprises a second delay circuit for delaying the (n-1)th clock in the phase sequence, and a circuit arrangement for generating an output clock phase having a delay time relative to the nth clock, being equal to an smaller value of one half clock width of the first basic clock minus a delay time of the first delay circuit and a delay time of the second delay circuit.

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patent: 4816700 (1989-03-01), Imel
patent: 5148050 (1992-09-01), Koide
patent: 5424668 (1995-01-01), Kohsaka

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