Clock generating circuit generating a plurality of clock...

Details Clock generating circuit generating a plurality of clock... Clock generating circuit generating a plurality of clock...

2002-05-06

2004-07-06

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S115000, C327S118000, C327S176000, C377S047000, C377S073000

Reexamination Certificate

active

06759886

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a clock generating circuit, and particularly, to a clock generating circuit generating a plurality of clock signals having different frequencies.
2. Description of the Background Art
Conventionally, a semiconductor integrated circuit device is provided with a clock generating circuit for generating a plurality of internal clock signals having different frequencies with aligned edges. A plurality of internal clock signals are used when a portion (e.g. a core unit) is operated at a high speed while another portion (e.g. a bus interface unit) is operated at a low speed within the semiconductor integrated circuit device, or when an internal circuit is operated at a high speed in a normal operation while it is operated at a low speed under light load in order to reduce power consumption.
FIG. 26
is a circuit block diagram showing the configuration of such a clock generating circuit. In
FIG. 26
, the dock generating circuit includes frequency-dividing circuits
81
to
83
, and buffers
84
to
87
. Frequency-dividing circuit
81
includes, as shown in
FIG. 27
, a selector
90
, a flip-flop
91
and an inverter
92
. Flip-flop
91
captures the level of an output signal &phgr;
90
of selector
90
in the period during which a reference clock signal CLKR is at a logic low or “L” level, and outputs the captured level in response to the rising edge of reference clock signal CLKR. Output clock signal CLK
1
of flip-flop
91
is applied to selector
90
via inverter
92
. Selector
90
applies a logic high or “H” level (a power-supply potential VCC) to flip-flop
91
when a reset signal /RST is at an activated level of “L” level, whereas it applies an output signal of inverter
92
to flip-flop
91
when reset signal /RST is at an inactivated level of “H” level.
In the period during which reset signal /RST is at the activated level of “L” level, output signal &phgr;
90
of selector
90
is fixed at “H” level, an output clock signal CLK
1
of flip-flop
91
is fixed at “H” level, and the output signal of inverter
92
is fixed at “L” level.
As shown in
FIG. 28
, when reset signal /RST is raised to be at the inactivated level of “H” level in synchronization with a rising edge (time t
0
) of reference clock signal CLKR, output signal &phgr;
90
of selector
90
is lowered to be at “L” level. A signal of “L” level is captured into flip-flop
91
in the period during which reference clock signal CLKR is at “L” level, and the captured signal of “L” level is output from flip-flop
91
in response to each rising edge of reference lock signal CLKR. The signal of “L” level output from flip-flop
91
is inverted at inverter
92
and then input into flip-flop
91
. Thus, output clock signal CLK
1
of flip-flop
91
is a signal obtained by dividing the frequency of reference clock signal CLKR by 1/2. Output clock signal CLK
1
of frequency-dividing circuit
81
is applied to an internal circuit of the semiconductor integrated circuit device via buffer
85
.
Frequency-dividing circuit
82
generates an internal clock signal CLK
2
by dividing the frequency of reference clock signal CLKR by 1/4. Frequency-dividing circuit
82
employs two stages of flip-flops as a substitute for flip-flop
91
of frequency-dividing circuit
81
. Output clock signal CLK
2
of frequency-dividing circuit
82
is applied to the internal circuit via buffer
86
.
Frequency-dividing circuit
83
generates an internal clock signal CLK
3
by dividing the frequency of reference clock signal CLKR by 1/8. Frequency-dividing circuit
83
employs three stages of flip-flops as a substitute for flip-flop
91
of frequency-dividing circuit
81
. Output clock signal CLK
3
of frequency-dividing circuit
83
is applied to the internal circuit via buffer
87
.
Moreover, reference clock signal CLKR is applied to the internal circuit via buffer
84
. Thus, a plurality of internal clock signals CLKR, and CLK
1
to CLK
3
having different frequencies are generated with the rising edges aligned (at time t
2
).
Such a clock generating circuit must use reset signal /RST to align the rising edges; otherwise the timing at which each of frequency-dividing circuits
81
to
83
starts the frequency-dividing would be different from one another.
However, for the use of reset signal /RST, it was necessary to externally input reset signal /RST, or to separately provide e.g. a power-on reset circuit for generating reset signal /RST. This resulted in problems such that the number of external pins for the semiconductor integrated circuit device is increased, and the circuit configuration is complicated.
SUMMARY OF THE INVENTION
Therefore, a main object of the present invention is to provide a clock generating circuit that can generate a plurality of clock signals having different frequencies with the edges aligned, without external introduction of a reset signal.
According to one aspect of the present invention, a clock generating circuit includes a plurality of stages of frequency-dividing circuits connected in series, of which a first stage receives a reference clock signal, the plurality of stages outputting the plurality of clock signals. Each of the frequency-dividing circuits includes a plurality of stages of flip-flops connected in series, of which an input terminal of a first stage receives a first potential, each flip-flop capturing a potential of an input terminal in a period during which an input clock signal of each frequency-dividing circuit is at a second potential, outputting the captured potential in response to a change of the input clock signal of each frequency-dividing circuit from the second potential to the first potential, and being reset in response to an output of the first potential from a last stage of the plurality of stages of flip-flops, to output the second potential. An output clock signal of a predetermined flip-flop of the plurality of flip-flops will be an output clock signal of each frequency-dividing circuit. Thus, the plurality of frequency-dividing circuits requiring no reset signal are connected in series, so that a plurality of clock signals having different frequencies with the edges aligned can be generated without external introduction of the reset signal.
According to another aspect of the present invention, a clock generating circuit includes a phase control circuit controlling a phase of an output clock signal such that a phase of a feedback clock signal coincides with a phase of a reference clock signal; and a plurality of stages of frequency-dividing circuits connected in series, of which a first stage receives an output clock signal of the phase control circuit, the plurality of stages outputting a plurality of clock signals, and of which a last stage provides an output dock signal which is also used as the feedback clock signal. Thus, the plurality of frequency-dividing circuits are connected in series, so that a plurality of clock signals having different frequencies with the edges aligned can be generated without external introduction of the reset signal.
Preferably, each of the frequency-dividing circuits includes a plurality of stages of flip-flops connected in series, of which an input terminal of a first stage receives a first potential, each flip-flop capturing a potential of an input terminal in a period during which an input clock signal of each frequency-dividing circuit is at a second potential, outputting the captured potential in response to a change of the input clock signal of each frequency-dividing circuit from the second potential to the first potential, and being reset in response to an output of the first potential from a last stage of the plurality of stages of flip-flops, to output the second potential. An output clock signal of a predetermined flip-flop of the plurality of flip-flops is an output clock signal of each frequency-dividing circuit. In this case, the frequency-dividing circuits requiring no reset signal are connected in series, so that a plurality of clock signals having different

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