Clock generating circuit for digital circuit operating in synchr

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating

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327298, H03B 506

Patent

active

057195170

ABSTRACT:
An oscillation stop signal holding latch 3 which stores a value deciding significant/unsignificant of an oscillation stop signal 4, and a NOR gate 21 which controls, when the oscillation stop signal 4 is significant, to stop the generation of a clock signal 7 and controls, when a predetermined signal is inputted from an input terminal 1 of an external signal in the abovementioned states with the oscillation stop signal being unsignificant, to resume the generation of the clock signal 7, and further a sampling circuit 10 between the input terminal 1 of the external signal and the oscillation stop signal holding latch 3 are provided. And a gate circuit 30 which forcibly makes the oscillation stop signal 4 become unsignificant so as to generate the clock signal 7 when the input signal from the input terminal 1 of the external signal is significant is provided. This enables the sampling circuit 10 to sample the input signal from the input terminal 1 of the external signal.

REFERENCES:
patent: 4518865 (1985-05-01), Iwasaki
patent: 4641044 (1987-02-01), Shiraishi
patent: 4736162 (1988-04-01), Ishihara
patent: 4886983 (1989-12-01), Taka
patent: 5151613 (1992-09-01), Satou et al.

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