Clock generating circuit ensuring a wide lock-allowing...

Details Clock generating circuit ensuring a wide lock-allowing... Clock generating circuit ensuring a wide lock-allowing...

2001-02-02

2002-08-20

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000, C365S189070

Reexamination Certificate

active

06438067

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a clock generating circuit used in a semiconductor memory device, and particularly relates to a clock generating circuit which generates an internal clock signal synchronized with an externally applied clock signal by means of a digital DLL (Delay Locked Loop) as well as a semiconductor memory device provided with the same.
2. Description of the Background Art
For generating a clock signal within a semiconductor memory device, such an technique has been known that a clock generating circuit (which will also be referred to merely as a “DLL circuit” hereinafter) employing the digital DLL is used for delaying a phase of an externally applied clock signal, and thereby the internal clock signal synchronized with the external clock is generated. This technique is particularly important in an SDRAM (Synchronous Dynamic Random Access Memory).
FIG. 12
is a block diagram showing a structure of a clock generating circuit
500
in the prior art employing the digital DLL.
Referring to
FIG. 12
, clock generating circuit
500
includes a delay circuit
510
which delays an input clock signal SIGIN of a cycle time Tcyc, a phase comparator circuit
520
which makes a comparison between phases of an output clock signal SIGOUT generated from delay circuit
510
and input clock signal SIGIN, and a delay control circuit
530
which controls the amount of delay of delay circuit
510
in accordance with the result of comparison of phase comparator circuit
520
.
Delay circuit
510
is also called a “delay line” and, for example, includes delay units
515
-
1
-
515
-
n
each providing a delay amount td. In this case, delay control circuit
530
operates in response to the result of phase comparison of phase comparator circuit
520
to increase or decrease the number of delay units to be activated in delay circuit
510
. In general, each of delay units
515
-
1
-
515
-
n
in delay circuit
510
employs a semiconductor element circuit such as an inverter, which is formed of field-effect transistors.
As described above, the total delay amount provided by delay circuit
510
is controlled in accordance with the result of phase comparison so that the output clock signal SIGOUT is delayed by the amount equal to one cycle time Tcyc from input clock signal SIGIN, whereby it is possible to produce the clock signal having the phase coincident with that of the input clock signal. In the following description, the state where the phases of the input and output clock signals are coincident with each other will also be referred to as a “locked state”.
In general, the clock generating circuit in the prior art uses a Voltage Down Converter (which will also be referred to merely as a “VDC” hereinafter) for stabilizing a drive potential Vc of these delay units so that delay amount td of each delay unit is set to a constant value. Additionally, the number of delay units to be activated is controlled. Thereby, the synchronized state is ensured.
However, in a field-effect transistor such as an MOS transistor forming an inverter, a channel resistance has a temperature dependency. More specifically, the channel resistance value is small in a low temperature region, and is large in a high temperature region.
In accordance with this characteristic, the inverter formed of the MOS transistors delays the signal by a small amount in the low temperature region, and delays it by a large amount in the high temperature region. Accordingly, the delay unit provides delay amount td, which is variable depending on the temperature region, and more specifically, provides delay amount td, which is small in the low temperature region, and is large in the high temperature region, even if the delay unit has the constant structure.
FIG. 13
conceptually shows a problem relating to temperature conditions of a clock generating circuit
500
in the prior art.
Referring to
FIG. 13
, temperatures Tn and Tx correspond to an operation-ensured range of clock generating circuit
500
. For example, the range between Tn and Tx corresponds to the operation specification temperature range of the semiconductor memory device provided with clock generating circuit
500
. In general, Tn is about −40° C., and Tx is about 120° C.
The ordinate gives the total delay amount which can be provided by delay circuit
510
in clock generating circuit
500
. After clock generating circuit
500
entered the locked state, the locked state must be maintained by adjusting the total delay amount of delay circuit
510
in clock generating circuit
500
. Accordingly, the total delay amount which can be applied by entire delay circuit
510
determines the lock-allowing frequency range, i.e., the frequency range allowing locking in clock generating circuit
500
.
In
FIG. 13
, delay amount DT
0
corresponds to the case where delay circuit
510
applies the minimum delay amount at minimum specified temperature Tn. In this case, the minimum number of delay units are activated. Delay amount DT
1
is a total delay amount in the case where the minimum number of delay units are activated at maximum specified temperature Tx.
Delay amount DT
2
is applied in the case where all the delay units are activated at minimum specified temperature Tn, and is given by n·td in connection with the number and amount in FIG.
12
. At the maximum specified temperature Tx, delay amount td per unit increases in accordance with increase in channel resistance caused by rise in temperature, and therefore the total delay amount, which is obtained by activating all the delay units, takes on a value of DT
3
larger than DT
2
. Frequencies f
0
-f
3
correspond to inverses of total delay amounts DT
0
-DT
3
, respectively, and establish a relationship of f
3
<f
2
<f
1
<f
0
.
The lock-allowing frequency range at maximum specified temperature Tx is between f
1
and f
3
, but the lock-allowing frequency range at minimum specified temperature Tn is between f
0
and f
2
, and therefore is significantly narrow. In a hatched region in
FIG. 13
, therefore, the total delay amount is not enough to synchronize the input and output clock signals with each other. As a result, only the range of f
1
-f
2
forms the lock-allowing operation frequency range in the whole range according to the operation specifications relating to the temperature.
As described above, the lock-allowing frequency range changes to a large extent particularly on the low frequency side in accordance with variations in temperature conditions. Therefore, clock generating circuit
500
in the prior art must be provided with an appropriate number of delay units, which are required for ensuring the operation frequency range on the low frequency side with respect to the minimum specified temperature. This causes a problem of increase in layout area.
SUMMARY OF THE INVENTION
An object of the invention is to provide a clock generating circuit which can ensure a wide lock-allowing frequency range while requiring a small layout area.
Another object of the invention is to provide a semiconductor memory device provided with a clock generating circuit which generates an internal clock signal in synchronization with an external clock signal, and can ensure a wide lock-allowing frequency range while requiring a small layout area.
In summary, a clock generating circuit includes a delay circuit, a phase comparator circuit, a drive potential control circuit and a delay control circuit.
The delay circuit delays the input clock signal and outputs the delayed input clock signal. The delay circuit includes a plurality of delay units for delaying the input clock signal by a first delay amount obtained by multiplying a first unit delay amount by L (L: a natural number), and the first unit delay amount changes in accordance with a drive potential of the plurality of delay units. The phase comparator circuit makes a comparison between phases of the input clock signal and the output signal of the delay circuit. The drive potential control circuit controls the drive potential

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