Clock generating circuit capable of generating internal...

Details Clock generating circuit capable of generating internal... Clock generating circuit capable of generating internal...

2003-02-07

2004-04-20

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S156000

Reexamination Certificate

active

06724228

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a clock generating circuit for generating an internal clock signal synchronized with an external clock signal, and more particularly to an internal clock generating circuit for generating an internal clock signal used at least for outputting data in a synchronous-type semiconductor memory device. More specifically, the present invention is related to a circuit for adjusting a delay amount of a DLL (Delay Locked Loop) for generating an internal clock signal synchronized in phase with an external clock signal by delaying the external clock signal.
2. Description of the Background Art
A clock synchronous semiconductor memory device for transferring data/signal in synchronization with a clock signal is widely used. In the clock synchronous semiconductor memory device, a skew of a signal/data is required to be considered only with respect to the clock signal, and it is unnecessary to consider a skew among signals, so that an internal operation start timing can be advanced. For example, data is transferred synchronously with a clock signal as a system clock, high-speed data transfer can be achieved and a bandwidth of data transfer can be widened.
As a clock synchronous semiconductor memory device, a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) for transferring data synchronously with the rising and falling edges of a clock signal is known.
FIG. 23
is a diagram showing data outputting timings of the DDR SDRAM. As shown in
FIG. 23
, output data Q
0
to Q
3
is successively outputted synchronously with the rising and falling edges of an external clock signal CLK. It is determined to output data DQ synchronously with the rising and falling edges of external clock signal CLK as a general standard of output timings of a DDR-SDRAM.
In the case of outputting data by using external clock signal CLK as a trigger, due to delay in a clock input buffer for generating an internal clock and a data output buffer for outputting data, output data is delayed with respect to external clock signal CLK, so that the general standard of data output cannot be satisfied.
Therefore, usually in a DDR-SDRAM, in order to generate a clock signal used for data output, a DLL (Delay Locked Loop) circuit is provided internally. The DLL circuit delays external clock signal CLK by using fixed delay and variable delay internally, thereby generating clock signals CLKP and CLKN for data output each leading in phase relative to external clock signal CLK.
FIG. 24
is a diagram schematically showing the general configuration of a conventional DLL circuit. In
FIG. 24
, a DLL circuit
900
is provided with a clock input buffer
890
for generating buffered clock signals BUFCLK and ZBUFCLK by buffering external complementary clock signals CLK and ZCLK.
DLL circuit
900
includes: an internal clock generating circuit
902
for generating internal clock signals CLKP and CLKN by delaying buffered clock signals BUFCLK and ZBUFCLK, respectively; a phase difference detecting circuit
904
for detecting a phase difference between internal clock signal CLKP and buffered clock signal BUFCLK and generating signals UP and DWN indicative of a detection result; and a phase control circuit
906
for controlling a delay amount of internal clock generating circuit
902
in accordance with phase detection signals UP and DWN from phase difference detecting circuit
904
.
Internal clock signal CLKP for data output is fed back, the phase of internal clock signal CLKP is compared with the phase of buffered clock signal BUFCLK in phase difference detecting circuit
904
, and a delay amount in internal clock generating circuit
902
is so adjusted as to minimize the phase difference. By adjusting the phase of internal clock signal CLKP for data output in consideration of delays in clock input buffer
890
and the data output buffer, the phase of external clock CLK and the phase of the data output can be made coincident with each other.
FIG. 25
is a diagram showing more specifically a configuration of DLL circuit
900
in FIG.
24
. In
FIG. 25
, phase difference detecting circuit
904
includes: a replica buffer
34
for delaying internal clock signal CLKP by a predetermined time; and a phase detector
35
for detecting the phase difference between a feedback clock signal FBCLK outputted from replica buffer
34
and buffered clock signal BUFCLK. Replica buffer
34
is provided to compensate for the delays in clock input buffer
890
and the data output buffer shown in FIG.
24
. Usually, clock input buffer
890
is constructed by a differential amplifier. In the case of detecting an intersecting portion of complementary external clock signals CLK and ZCLK and generating buffered clock signals BUFCLK and ZBUFCLK, the delay in clock input buffer
890
is neglected.
Phase detector
35
outputs phase detection result indicating signals UP and DWN in accordance with a result of phase comparison between feedback clock signal FBCLK and buffered clock signal BUFCLK. If feedback clock signal FBCLK leads in phase the buffered clock signal BUFCLK, up instruction signal UP is set to the H level in order to increase the delay amount of internal clock signals CLKP and CLKN. On the contrary, where feedback clock signal FBCLK lags in phase behind buffered clock signal BUFCLK, in order to advance the phases of internal clock signals CLKP and CLKN, down instruction signal DWN is set to the H level.
The delay amount of internal clock signal CLKP is increased by up instruction signal UP and is decreased by down instruction signal DWN.
Phase control circuit
906
includes: a counting circuit
307
for performing a counting operation in accordance with output signals UP and DWN of phase detector
35
; and a count control circuit
41
for controlling the minimum count value of counting circuit
37
upon power up or system reset. According to a count A[N:
0
] of counting circuit
37
, the delay amount of each of internal clock signals CLKP and CLKN is set.
Internal clock generating circuit
902
includes: a variable delay line
32
for generating internal clock signal CLKP by delaying buffered clock signal BUFCLK; and a variable delay line
33
for generating internal clock signal CLKN by delaying buffered clock signal ZBUFCLK. Count A[N:
0
] of counting circuit
37
is commonly supplied to variable delay lines
32
and
33
. Count circuit
37
is a bidirectional counter. The count of counting circuit
37
is increased when up instruction signal UP outputted from phase detector
35
is activated, and is decreased when down instruction signal DWN outputted from phase detector
35
is activated. The delay amount of each of variable delay lines
32
and
33
is set by the count of counting circuit
37
. When count A[N:
0
] increases, the delay amounts of variable delay lines
32
and
33
increase.
Count control circuit
41
controls the counting operation of counting circuit
37
by an enable signal EN. When enable signal EN is set to the H level, counting circuit
37
performs the counting operation. When enable signal EN is set to the L level, the counting operation is stopped. For example, in a power down mode or the like, the counting operation of counting circuit
37
is stopped to reduce current consumption.
FIGS. 26A and 26B
are diagrams illustrating the phase detecting operation of phase detector
35
shown in FIG.
25
. Phase detector
35
generates output signals UP and DWN so that the phase of feedback clock signal FBCLK and the phase of buffered clock signal BUFCLK coincide with each other. Signals UP and DWN are signals complementary to each other. The phase detection timing is the rising edge of buffered clock signal BUFCLK.
In
FIG. 26A
, if feedback clock signal FBCLK is at the L level at the rising edge of buffered clock signal BUFCLK, the phase of feedback clock signal FBCLK has to be advanced. In this case, therefore, down instruction signal DWN from phase detector
35
is set to the H level, and the delay amoun

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