Clock generating circuit by using the phase difference between a

Details Clock generating circuit by using the phase difference between a Clock generating circuit by using the phase difference between a

1994-09-01

1998-04-28

Psitos, Aristotelis M.

Dynamic magnetic information storage or retrieval

General processing of a digital signal

Data clocking

386 13, 386 85, 331 20, G11B 509

Patent

active

057453144

ABSTRACT:
A circuit for generating a clock of a predetermined frequency in folllowing-up relation to an input video signal, comprising a PLL circuit including a phase comparison circuit for comparing the phase of a synchronizing signal of the video signal with the phase of a feedback clock corresponding to the clock, and a control circuit for causing the feedback clock in the PLL circuit to be synchronized with the synchronizing signal.

REFERENCES:
patent: 3815042 (1974-06-01), Maunsell et al.
patent: 4092672 (1978-05-01), Aschwaden
patent: 4380743 (1983-04-01), Underhill et al.
patent: 4613827 (1986-09-01), Takamori et al.
patent: 4675724 (1987-06-01), Wagner
patent: 4680651 (1987-07-01), Blessinger
patent: 4692914 (1987-09-01), Yasumura et al.
patent: 4812783 (1989-03-01), Honjo et al.
patent: 5142420 (1992-08-01), Tanaka et al.

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