Clock generating circuit and clock generating method

Details Clock generating circuit and clock generating method Clock generating circuit and clock generating method

2005-05-03

2005-05-03

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S107000

Reexamination Certificate

active

06888391

ABSTRACT:
A clock generating circuit (100) that may prevent an erroneous clock signal from being provided to an internal logic circuit (105) has been disclosed. A clock generating circuit (100) may include a variable voltage generating circuit (101), an oscillating circuit (103), and a control circuit (104). Oscillating circuit (103) may provide an original clock signal (157). A charging circuit (122, 123, and124) may provide charging of a signal (159) when an original clock signal (157) achieves a predetermined amplitude. When signal (157) charges sufficiently, an oscillation stabilization signal may be provided to enable the generation of a synthesized clock signal (160). Also, at this time, a reduced voltage (170) may be provided to power an oscillating circuit (103). In this way, current consumption may be reduced and failures due to providing an erroneous clock signal to an internal logic circuit may be reduced.

REFERENCES:
patent: 3737790 (1973-06-01), Brown
patent: 4065721 (1977-12-01), Rabe
patent: RE34750 (1994-10-01), Ohmori
patent: 6545518 (2003-04-01), Saeki
patent: 195 34 785 C 1 (1997-01-01), None
patent: 696 09 488 T 2 (1997-11-01), None
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patent: 08-204450 (1996-08-01), None
patent: 10-004347 (1998-01-01), None
patent: 2000-293258 (2000-10-01), None
English translation of the above-mentioned office action.

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