Clock generating circuit

Details Clock generating circuit Clock generating circuit

2007-07-03

2007-07-03

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S291000, C327S327000, C327S271000

Reexamination Certificate

active

11206142

ABSTRACT:
A clock generating circuit includes a first delay circuit array, which has a plurality of delay circuits, for measuring delay of an input signal, and a second delay circuit array for delay-replay having a plurality of delay circuits and being arranged in a direction opposite a direction of signal propagation in the first delay circuit array. On the basis of a signal that is output from a delay circuit at a position where a delay has been detected in the first delay circuit array, an output terminal of a delay circuit in the second delay circuit array that corresponds to the position where the delay has been detected in the first delay circuit array is fed back to an input terminal of this delay circuit to thereby construct a closed loop and form a ring oscillator circuit. An oscillation output signal of the ring oscillator circuit is extracted from an output terminal of the second delay circuit array. Two phase interpolators are provided on the input end of the first delay circuit array for variably controlling the phase of the output signal relative to the input signal. The first delay circuit array measures the phase difference between the output signals of the two phase interpolators.

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