Clock generating circuit

Details Clock generating circuit Clock generating circuit

2006-08-08

2006-08-08

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S156000, C327S147000

Reexamination Certificate

active

07088155

ABSTRACT:
In a clock generation circuit generating a clock that is synchronized with a reference signal, it is an object to provide stable clocks by controlling phase jitter in a generated clock upon change of the reference signal, eliminate a stable-state phase difference between the reference signal and the generated clock so that control is eliminated, and allow the clock generation circuit to be integrated. The clock generation circuit is configured with multiple stages of PLL circuits such that PLL circuits2are provided for reference signals1, respectively, and one of outputs from the PLL circuits2is selected to be fed to a PLL circuit5provided in a next stage. The phase fluctuation of a signal inputted to the PLL circuit5upon change of the reference signal1is reduced to control the phase jitter of the generated clock6, thus allowing high loop gain in both the PLL circuit2and the PLL circuit5. Then, phase difference between the reference signal1and the generated clock6is eliminated to eliminate control involved, so that the clock generation circuit may be integrated.

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