Clock generating circuit

Details Clock generating circuit Clock generating circuit

2003-01-23

2004-08-24

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S295000, C331S057000

Reexamination Certificate

active

06781431

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a clock generating circuit and particularly, to a clock generating circuit that generates a clock signal when an activating signal is at a first level, while ceasing generation of a clock signal when the activating signal is at a second level.
2. Description of the Background Art
A dynamic random access memory (hereinafter referred to as DRAM) has been mainly fabricated in a CMOS process, wherein memory cells thereof are each constructed from an N channel MOS transistor and a capacitor. When data is written onto a memory cell, a boosted potential Vpp higher than a normal H level (external power source potential ExVdd) is applied to the gate of the N channel MOS transistor in order to prevent a potential drop in the N channel MOS transistor. For this reason, a boosted potential generating circuit for generating the boosted potential Vpp from the external power source potential ExVdd is incorporated in DRAM.
FIG. 11
is a circuit block diagram representing a main part of such a boosted potential generating circuit.
In
FIG. 11
, the boosted potential generating circuit includes: a clock generating circuit
50
; and a charge pump circuit
51
. The clock generating circuit
50
, as shown in
FIG. 12
, includes: a NAND gate
55
and inverters
56
and
57
. The inverters
56
and
57
are connected in series between the output node of the NAND gate
55
and one input node thereof. The other input node thereof receives an activating signal &phgr;EN. The activating signal &phgr;EN goes to H level when the boosted potential Vpp is lower than a target potential Vt, while the activating signal &phgr;EN goes to L level when the boosted potential Vpp is higher than the target potential Vt. An output signal of the NAND gate
55
serves as a clock signal CLK.
When the activating signal &phgr;EN is at H level, the NAND gate
55
acts as an inverter for an output signal of the inverter
57
, and the NAND gate
55
and the inverters
56
and
57
constitutes a ring oscillator. Hence, a level of the clock signal CLK is inverted each time when a delay time of the NAND gate and the inverters
56
and
57
elapses. When the activating signal &phgr;EN goes to L level, an output level of the NAND gate
55
is fixed at H level.
Returning to
FIG. 11
, the charge pump circuit
51
includes: diodes
52
and
53
; and a capacitor
54
. The diodes
52
and
53
are connected in series between an external power source potential ExVdd line and an output node N
53
. One terminal of the capacitor
54
receives the clock signal CLK, while the other terminal thereof is connected to the cathode (node N
52
) of the diode
52
.
FIG. 13
is a time chart representing operation of the boosted potential generating circuit shown in FIG.
11
. It is assumed that in an initial state, the boosted potential Vpp is sufficiently lower than the target potential Vt, the activating signal &phgr;EN is forced to go to H level to activate the clock generating circuit
50
, thus inverting a level of the clock signal CLK after each elapse of a prescribed time.
During a period in which the clock signal CLK is at L level (ground potential GND), a current flows into the capacitor
54
from the external power source potential ExVdd line through the diode
52
, and the capacitor
54
is precharged to ExVdd−Vd, wherein Vd indicates threshold voltages of the respective diodes
52
and
53
.
When the clock signal CLK is raised to H level (ExVdd) following the precharge, a level of the node N
52
is boosted to 2ExVdd−Vd through the capacitor
54
and a positive electric charge is supplied to the output node N
53
from the node N
52
. A level of the node N
52
comes to be Vpp+Vd.
That is, when the activating signal &phgr;EN is at H level, the capacitor
54
is charged during a period in which the clock signal CLK (precharge period) is at L level, while a charge of the capacitor
50
is supplied to the output node N
53
during a period in which the clock CLK is at H level (pump period) to boost a potential of the output node N
53
.
When the boosted potential Vpp reaches the target potential Vt and the activating signal &phgr;EN goes to L level, a level of the clock signal CLK is fixed at H level and the charge pump circuit
51
is deactivated. When the boosted potential Vpp falls to be lower than the target potential Vt, the activating signal &phgr;EN goes to H level to again activate the charge pump circuit
51
. Hence, the boosted potential Vpp is held at the target potential Vt.
There was a problem, however, since in a prior art boosted potential generating circuit, when, as shown in
FIG. 14
, the boosted potential Vpp reaches the target potential Vt in a period in which the clock signal CLK is at L level and the activating signal &phgr;EN is lowered from H level to L level, then the clock signal CLK is raised to H level in response to the falling edge of the activating signal &phgr;EN and thereby, there arises a so-called glitch G in the clock signal CLK. When such a glitch arises, the charge pump circuit
51
again supplies a positive electric charge in response to the rise of the clock signal CLK and the boosted potential Vpp rises excessively higher than the target potential Vt, even though the boosted potential Vpp has reached the target potential Vt.
SUMMARY OF THE INVENTION
It is accordingly a main object of the present invention is to provide a clock generating circuit capable of preventing generation of a glitch.
In a clock generating circuit relating to the present invention, included are: an oscillator generating a reference clock signal; a first latch circuit, provided between a first and second nodes, and operating in synchronism with the reference clock signal; a second latch circuit, provided between the second node and an output node, and operating in synchronism with a complementary signal of the reference clock signal; and a logic circuit, provided between the output node and the first node, and providing a complementary level of a level on the output node to the first node to generate a clock signal when an activating signal is at a first level, while transmitting a level on the output node to the first node to cease generation of the clock signal when the activating signal is at a second level. Hence, since the clock signal is generated by frequency dividing the reference clock signal with the two latch circuits and the logic circuit, generation of a glitch in the clock signal can be prevented from occurring.
It is preferable that a noise filter for eliminating noise from an output signal of the logic circuit to provide the output signal to the first node is further provided between the output node of the logic circuit and the first node. In this case, even when noise occurs in an output signal of the logic circuit, generation of a glitch in the clock signal can be prevented from occurring.
It is further preferable that the oscillator is activated in response to transition of the activation signal to the first level, while being deactivated in response to transition thereof to the second level. In this case, since when the reference clock signal is unnecessary, the oscillator is deactivated, power consumption can be reduced.
It is still further preferable that further provided is a delay circuit delaying the activating signal by a prescribed time to provide the activating signal to the oscillator. In this case, even when a glitch occurs in the reference clock signal, generation of a glitch in the clock signal can be prevented from occurring since a frequency dividing circuit constructed from the two latch circuits and the logic circuit has ceased a frequency dividing operation in advance.
In another clock generating circuit relating to the present invention, included are: a ring oscillator including an odd number of first inverters connected in a ring configuration, being activated to generate a clock signal when an activating signal is at a first level, while being deactivated to cease generation of the clock signa

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