Clock-gating circuit insertion method, clock-gating circuit...

Details Clock-gating circuit insertion method, clock-gating circuit... Clock-gating circuit insertion method, clock-gating circuit...

2011-04-12

2011-04-12

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C716S113000

Reexamination Certificate

active

07926014

ABSTRACT:
A clock-gating circuit insertion method includes inserting a clock-gating circuit into a position detected on the basis of a circuit data. Timing analysis of an enable signal is performed for the clock-gating circuit. An upper limit of delay variations for the enable signal is calculated to satisfy setup conditions on the basis of the result of the timing analysis. A selector-equipped clock-gating circuit including a selector circuit and a clock-gating circuit is inserted into the candidate position for insertion. The selector circuit selects and outputs the enable signal when delay variations are not above the upper limit. The selector circuit selects and outputs a signal designating the passing of a clock signal when the delay variations are above the upper limit. The clock-gating circuit passes or intercepts the clock signal on the basis of the output signal of the selector circuit.

REFERENCES:
patent: 6272667 (2001-08-01), Minami et al.
patent: 6318911 (2001-11-01), Kitahara
patent: 6668363 (2003-12-01), Minami et al.
patent: 7197725 (2007-03-01), Takeoka et al.
patent: 2001/0029599 (2001-10-01), Minami et al.
patent: 2002-190528 (2002-07-01), None
patent: 10-283381 (2008-10-01), None

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